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8k isp flash mcu family c8051f020/1/2/3 preliminary rev. 1.4 12/03 copyright ? 2003 by silicon laboratories c8051f020/1/2/3-ds14 this information applies to a product under development. its charac teristics and specifications ar e subject to change without n otice. analog peripherals - sar adc ? 12-bit (c8051f020/1) ? 10-bit (c8051f022/3) ? 1 lsb inl ? programmable throughput up to 100 ksps ? up to 8 external inputs; programmable as single-ended or differential ? programmable amplifier gain: 16, 8, 4, 2, 1, 0.5 ? data-dependent windowed interrupt generator ? built-in temperature sensor ( 3c) - 8-bit adc ? programmable throughput up to 500 ksps ? 8 external inputs ? programmable amplifier gain: 4, 2, 1, 0.5 - two 12-bit dacs ? can synchronize outputs to timers for jitter-free wave - form generation - two analog comparators - voltage reference - precision vdd monitor/brown-out detector on-chip jtag debug & boundary scan - on-chip debug circuitry faci litates full- speed, non- intrusive in-circu it/in-syste m debugging - provides breakpoints, singl e-stepping, watchpoints, stack monitor; inspect/modi fy memory and registers - superior performance to em ulation systems using ice- chips, target pods, and sockets - ieee1149.1 compliant boundary scan - low-cost, complete development kit high speed 8051 c core - pipelined instruction archite cture; executes 70% of instruction set in 1 or 2 system clocks - up to 25 mips throughput with 25 mhz clock - 22 vectored interrupt sources memory - 4352 bytes internal data ram (4k + 256) - 64k bytes flash; in-system programmable in 512-byte sectors - external 64k byte data me mory interface (programma - ble multiplexed or non-multiplexed modes) digital peripherals - 8 byte-wide port i/o (c8051f020/2); 5v tolerant - 4 byte-wide port i/o (c8051f021/3); 5v tolerant - hardware smbus? (i 2 c? compatible), spi?, and two uart serial ports available concurrently - programmable 16-bit counter/timer array with 5 capture/compare modules - 5 general purpose 16-bit counter/timers - dedicated watch-dog timer; bi-directional reset pin clock sources - internal programmable oscillator: 2-to-16 mhz - external oscillator: crys tal, rc, c, or clock - real-time clock mode using timer 3 or pca supply voltage .......................... 2.7v to 3.6v - typical operating current: 10 ma @ 20 mhz - multiple power saving sl eep and shutdown modes 100-pin tqfp and 64-pin tqfp packages available temperature range: -40c to +85c jtag 64kb isp flash 4352 b sram sanity control + - 10/12-bit 100ksps adc clock circuit pga vref 12-bit dac temp sensor voltage comparators analog peripherals port 0 port 1 port 2 port 3 crossbar digital i/o high-speed controller core debug circuitry 22 interrupts 8051 cpu (25mips) 12-bit dac + - 8-bit 500ksps adc port 4 port 5 port 6 port 7 external memory interface 100 pin 64 pin pga uart0 smbus spi bus pca timer 0 timer 1 timer 2 timer 3 timer 4 uart1 amux amux
c8051f020/1/2/3 2 rev. 1.4 notes
c8051f020/1/2/3 rev. 1.4 3 table of contents 1. system over view .........................................................................................................17 1.1. cip-51? microcontr oller core ......................................................................................22 1.1.1. fully 8051 compatible ..........................................................................................22 1.1.2. improved thr oughput ............................................................................................22 1.1.3. additional feat ures................................................................................................23 1.2. on-chip memory ............................................................................................................2 4 1.3. jtag debug and boundary scan ...................................................................................25 1.4. programmable digital i/o and cro ssbar .........................................................................26 1.5. programmable counter array .........................................................................................27 1.6. serial ports............................................................................................................... ........27 1.7. 12-bit analog to digi tal converter.................................................................................28 1.8. 8-bit analog to digi tal converter...................................................................................29 1.9. comparators and dacs...................................................................................................30 2. absolute maximum ratings ..................................................................................31 3. global dc electrical characteristics ......................................................32 4. pinout and package definitions........................................................................33 5. adc0 (12-bit adc, c8051f020/1 only) ........................................................................43 5.1. analog multiplexer and pga..........................................................................................43 5.2. adc modes of op eration ...............................................................................................44 5.2.1. starting a conversion.............................................................................................44 5.2.2. tracking modes .....................................................................................................45 5.2.3. settling time requirements ..................................................................................46 5.3. adc0 programmable wi ndow detector.........................................................................53 6. adc0 (10-bit adc, c8051f022/3 only) ........................................................................59 6.1. analog multiplexer and pga..........................................................................................59 6.2. adc modes of op eration ...............................................................................................60 6.2.1. starting a conversion.............................................................................................60 6.2.2. tracking modes .....................................................................................................61 6.2.3. settling time requirements ..................................................................................62 6.3. adc0 programmable wi ndow detector.........................................................................69 7. adc1 (8-bit adc) ............................................................................................................. ..75 7.1. analog multiplexer and pga..........................................................................................75 7.2. adc1 modes of op eration .............................................................................................76 7.2.1. starting a conversion.............................................................................................76 7.2.2. tracking modes .....................................................................................................76 7.2.3. settling time requirements ..................................................................................78 8. dacs, 12-bit voltage mode ......................................................................................83 8.1. dac output sche duling..................................................................................................83 8.1.1. update output on-demand ...................................................................................84 8.1.2. update output based on timer overflow .............................................................84 8.2. dac output scaling/ justification...................................................................................84 9. voltage referenc e (c8051f020/2)..........................................................................91
c8051f020/1/2/3 4 rev. 1.4 10. voltage referenc e (c8051f021/3)..........................................................................93 11. comparators................................................................................................................. .95 12. cip-51 microcon troller........................................................................................101 12.1. instruction set........................................................................................................... .....102 12.1.1. instruction and cpu timing................................................................................102 12.1.2. movx instruction and program memory...........................................................102 12.2. memory organi zation ...................................................................................................107 12.2.1. program memory .................................................................................................107 12.2.2. data memory .......................................................................................................108 12.2.3. general purpose registers ...................................................................................108 12.2.4. bit addressable locations ...................................................................................108 12.2.5. stack .................................................................................................................10 8 12.2.6. special function registers...................................................................................109 12.2.7. register descri ptions ...........................................................................................113 12.3.interrupt ha ndler ......................................................................................................... ..116 12.3.1. mcu interrupt sources and vectors ...................................................................116 12.3.2. external inte rrupts ...............................................................................................116 12.3.3. interrupt prio rities................................................................................................118 12.3.4. interrupt late ncy..................................................................................................118 12.3.5. interrupt register descriptions ............................................................................119 12.4. power management modes ...........................................................................................125 12.4.1. idle mode .............................................................................................................12 5 12.4.2. stop mode............................................................................................................125 13. reset sources ..............................................................................................................1 27 13.1. power-on reset............................................................................................................ ..128 13.2. power-fail re set .......................................................................................................... ..128 13.3. external reset............................................................................................................ ....129 13.4. software forced reset...................................................................................................12 9 13.5. missing clock detect or reset .......................................................................................129 13.6. comparator0 re set ........................................................................................................1 29 13.7. external cnvstr pin reset .........................................................................................129 13.8. watchdog timer reset ..................................................................................................129 13.8.1. enable/reset wdt ..............................................................................................130 13.8.2. disable wdt .......................................................................................................130 13.8.3. disable wdt lo ckout.........................................................................................130 13.8.4. setting wdt in terval...........................................................................................130 14. oscillators................................................................................................................. ..135 14.1.external crystal example..............................................................................................138 14.2. external rc ex ample ....................................................................................................138 14.3.external capacito r example..........................................................................................138 15. flash memory ..............................................................................................................13 9 15.1. programming the flash memory .............................................................................139 15.2. non-volatile data storage .............................................................................................140 15.3. security options .......................................................................................................... ..140 16. external data memory inter face and on-chip xram.......................145
c8051f020/1/2/3 rev. 1.4 5 16.1. accessing xr am..........................................................................................................14 5 16.1.1. 16-bit movx exam ple.......................................................................................145 16.1.2. 8-bit movx ex ample.........................................................................................145 16.2. configuring the external memory interface .................................................................146 16.3. port selection and configuration ..................................................................................146 16.4. multiplexed and non-mult iplexed selection.................................................................148 16.4.1. multiplexed conf iguration ..................................................................................148 16.4.2. non-multiplexed configuration...........................................................................149 16.5. memory mode se lection ...............................................................................................150 16.5.1. internal xram only ...........................................................................................150 16.5.2. split mode without bank select ..........................................................................150 16.5.3. split mode with bank select ...............................................................................151 16.5.4. external on ly .......................................................................................................151 16.6. timing .................................................................................................................... ...151 16.6.1. non-multiplexe d mode........................................................................................153 16.6.1.1. 16-bit movx: emi0cf[4:2] = ?101?, ?110?, or ?111?................................153 16.6.1.2. 8-bit movx without bank select: em i0cf[4:2] = ?101? or ?111?............154 16.6.1.3. 8-bit movx with bank sele ct: emi0cf[4:2] = ?110?. ..............................155 16.6.2. multiplexed mode................................................................................................156 16.6.2.1. 16-bit movx: emi0cf[4:2] = ?001?, ?010?, or ?011?................................156 16.6.2.2. 8-bit movx without bank select: em i0cf[4:2] = ?001? or ?011?............157 16.6.2.3. 8-bit movx with bank sele ct: emi0cf[4:2] = ?010?. ..............................158 17. port input/ou tput .....................................................................................................161 17.1. ports 0 through 3 and the priori ty crossbar decoder....................................................163 17.1.1. crossbar pin assignment and allocation ............................................................163 17.1.2. configuring the output mode s of the port pins ..................................................164 17.1.3. configuring port pins as digital inputs ...............................................................165 17.1.4. external interrupts (ie6 and ie7) ........................................................................165 17.1.5. weak pull- ups......................................................................................................165 17.1.6. configuring port 1 pins as analog inputs (ain1.[7:0])......................................165 17.1.7. external memory interf ace pin assignments ......................................................166 17.1.8. crossbar pin assign ment example......................................................................168 17.2. ports 4 through 7 (c8051f020/2 only)..........................................................................177 17.2.1. configuring ports which are not pinned out.......................................................177 17.2.2. configuring the output mode s of the port pins ..................................................177 17.2.3. configuring port pins as digital inputs ...............................................................178 17.2.4. weak pull- ups......................................................................................................178 17.2.5. external memory interface ..................................................................................178 18. system managemen t bus / i2c bus (smbus0) .................................................183 18.1. supporting docume nts ..................................................................................................184 18.2. smbus protocol............................................................................................................ .185 18.2.1. arbitratio n............................................................................................................1 85 18.2.2. clock low exte nsion...........................................................................................185 18.2.3. scl low timeout ...............................................................................................186 18.2.4. scl high (smbus fr ee) timeout.......................................................................186
c8051f020/1/2/3 6 rev. 1.4 18.3. smbus transfer modes.................................................................................................187 18.3.1. master transmitter mode ....................................................................................187 18.3.2. master receiver mode.........................................................................................187 18.3.3. slave transmitter mode.......................................................................................188 18.3.4. slave receiver mode ...........................................................................................188 18.4. smbus special function registers ...............................................................................189 18.4.1. control register ...................................................................................................189 18.4.2. clock rate re gister .............................................................................................192 18.4.3. data regist er........................................................................................................193 18.4.4. address regi ster ..................................................................................................193 18.4.5. status register .....................................................................................................194 19. serial peripheral inter face bus (spi0) ........................................................197 19.1. signal descri ptions....................................................................................................... .198 19.1.1. master out, slave in (mosi) ..............................................................................198 19.1.2. master in, slave out (miso) ..............................................................................198 19.1.3. serial clock (sck) ..............................................................................................198 19.1.4. slave select (nss)...............................................................................................198 19.2. spi0 operation ............................................................................................................ ..199 19.3. serial clock timing ......................................................................................................2 00 19.4. spi special function registers .....................................................................................201 20. uart0 ....................................................................................................................... ...........205 20.1. uart0 operationa l modes ..........................................................................................206 20.1.1. mode 0: synchronous mode................................................................................206 20.1.2. mode 1: 8-bit uart, variable baud rate .........................................................207 20.1.3. mode 2: 9-bit uart, fixed baud rate ..............................................................208 20.1.4. mode 3: 9-bit uart, variable baud rate .........................................................209 20.2. multiprocessor co mmunications...................................................................................210 20.3. frame and transmission error detection......................................................................211 21. uart1 ....................................................................................................................... ...........215 21.1. uart1 operationa l modes ..........................................................................................216 21.1.1. mode 0: synchronous mode................................................................................216 21.1.2. mode 1: 8-bit uart, variable baud rate .........................................................217 21.1.3. mode 2: 9-bit uart, fixed baud rate ..............................................................218 21.1.4. mode 3: 9-bit uart, variable baud rate .........................................................219 21.2. multiprocessor co mmunications...................................................................................220 21.3. frame and transmission error detection......................................................................221 22. timers...................................................................................................................... ..........225 22.1. timer 0 and timer 1......................................................................................................2 27 22.1.1. mode 0: 13-bit co unter/timer.............................................................................227 22.1.2. mode 1: 16-bit co unter/timer.............................................................................228 22.1.3. mode 2: 8-bit counter/time r with auto-reload .................................................229 22.1.4. mode 3: two 8-bit counter/t imers (timer 0 only) ...........................................230 22.2. timer 2 ................................................................................................................... ....234 22.2.1. mode 0: 16-bit counter/tim er with capture .......................................................235 22.2.2. mode 1: 16-bit counter/tim er with auto-reload ...............................................236
c8051f020/1/2/3 rev. 1.4 7 22.2.3. mode 2: baud rate generator .............................................................................237 22.3. timer 3 ................................................................................................................... ....240 22.4. timer 4 ................................................................................................................... ....243 22.4.1. mode 0: 16-bit counter/tim er with capture .......................................................244 22.4.2. mode 1: 16-bit counter/tim er with auto-reload ...............................................245 22.4.3. mode 2: baud rate generator .............................................................................246 23. programmable co unter array .......................................................................249 23.1. pca counter/t imer.......................................................................................................25 0 23.2. capture/compare modules............................................................................................252 23.2.1. edge-triggered capture mode .............................................................................253 23.2.2. software timer (c ompare) mode........................................................................254 23.2.3. high speed output mode ....................................................................................255 23.2.4. frequency output mode ......................................................................................256 23.2.5. 8-bit pulse width m odulator mode ....................................................................257 23.2.6. 16-bit pulse width m odulator mode ..................................................................258 23.3. register descriptions for pca0 ....................................................................................259 24. jtag (ieee 1149.1).......................................................................................................... ..265 24.1. boundary scan............................................................................................................. ..266 24.1.1. extest instruction ............................................................................................267 24.1.2. sample instruct ion ...........................................................................................267 24.1.3. bypass instruction ............................................................................................267 24.1.4. idcode instruction ............................................................................................267 24.2. flash programming commands ....................................................................................268 24.3. debug support............................................................................................................. ..271
c8051f020/1/2/3 8 rev. 1.4 notes
c8051f020/1/2/3 rev. 1.4 9 list of figures and tables 1. system over view .........................................................................................................17 table 1.1. product sel ection guide ......................................................................................17 figure 1.1. c8051f020 bloc k diagram.................................................................................18 figure 1.2. c8051f021 bloc k diagram.................................................................................19 figure 1.3. c8051f022 bloc k diagram.................................................................................20 figure 1.4. C8051F023 bloc k diagram.................................................................................21 figure 1.5. comparison of peak mcu execution speeds.....................................................22 figure 1.6. on-board cl ock and reset..................................................................................23 figure 1.7. on-chip memory map ........................................................................................24 figure 1.8. development/in-s ystem debug diagram ...........................................................25 figure 1.9. digital crossbar diagram....................................................................................26 figure 1.10. pca block diagram............................................................................................27 figure 1.11. 12-bit adc block diagram................................................................................28 figure 1.12. 8-bit adc diagram ..... .......................................................................................29 figure 1.13. comparator and dac diagram...........................................................................30 2. absolute maximum ratings ..................................................................................31 table 2.1. absolute maximum ratings*..............................................................................31 3. global dc electrical characteristics ......................................................32 table 3.1. global dc electrica l characteristics...................................................................32 4. pinout and package definitions........................................................................33 table 4.1. pin defi nitions..................................................................................................... 33 figure 4.1. tqfp-100 pinout diagram..................................................................................38 figure 4.2. tqfp-100 package drawing...............................................................................39 figure 4.3. tqfp-64 pinout diagram....................................................................................40 figure 4.4. tqfp-64 package drawing.................................................................................41 5. adc0 (12-bit adc, c8051f020/1 only) ........................................................................43 figure 5.1. 12-bit adc0 functi onal block diag ram............................................................43 figure 5.2. temperature sensor transfer function ...............................................................44 figure 5.3. 12-bit adc track and conversion example timing.........................................45 figure 5.4. adc0 equivalent input circuits .........................................................................46 figure 5.5. amx0cf: amux0 configur ation register (c8051f020/1) .............................47 figure 5.6. amx0sl: amux0 channel se lect register (c8051f020/1)............................48 figure 5.7. adc0cf: adc0 configur ation register (c8051f020/1)..................................49 figure 5.8. adc0cn: adc0 control register (c8051f020/1) ...........................................50 figure 5.9. adc0h: adc0 data word msb register (c8051f020/1) ...............................51 figure 5.10. adc0l: adc0 data wo rd lsb register (c8051f020/1).................................51 figure 5.11. adc0 data word example (c8051f020/1) .......................................................52 figure 5.12. adc0gth: adc0 greater-than da ta high byte register (c8051f020/1) .....53 figure 5.13. adc0gtl: adc0 greater-than data low byte register (c8051f020/1) ......53 figure 5.14. adc0lth: adc0 less-than data high byte register (c8051f020/1) ..........53 figure 5.15. adc0ltl: adc0 less-than data low byte register (c8051f020/1) ...........53 figure 5.16. 12-bit adc0 window interrupt exam ple: right justified single-ended data .54
c8051f020/1/2/3 10 rev. 1.4 figure 5.17. 12-bit adc0 window interrupt exam ple: right justified differential data.....55 figure 5.18. 12-bit adc0 window interrupt exam ple: left justified single-ended data....56 figure 5.19. 12-bit adc0 window interrupt exam ple: left justified differential data.......57 table 5.1. 12-bit adc0 electrical ch aracteristics (c8051f020/1).....................................58 6. adc0 (10-bit adc, c8051f022/3 only) ........................................................................59 figure 6.1. 10-bit adc0 functi onal block diag ram............................................................59 figure 6.2. temperature sensor transfer function ...............................................................60 figure 6.3. 10-bit adc track and conversion example timing.........................................61 figure 6.4. adc0 equivalent input circuits .........................................................................62 figure 6.5. amx0cf: amux0 configur ation register (c8051f022/3) .............................63 figure 6.6. amx0sl: amux0 channel se lect register (c8051f022/3)............................64 figure 6.7. adc0cf: adc0 configur ation register (c8051f022/3)..................................65 figure 6.8. adc0cn: adc0 control register (c8051f022/3) ...........................................66 figure 6.9. adc0h: adc0 data word msb register (c8051f022/3) ...............................67 figure 6.10. adc0l: adc0 data wo rd lsb register (c8051f022/3).................................67 figure 6.11. adc0 data word example (c8051f022/3) .......................................................68 figure 6.12. adc0gth: adc0 greater-than da ta high byte register (c8051f022/3) .....69 figure 6.13. adc0gtl: adc0 greater-than data low byte register (c8051f022/3) ......69 figure 6.14. adc0lth: adc0 less-than data high byte register (c8051f022/3) ..........69 figure 6.15. adc0ltl: adc0 less-than data low byte register (c8051f022/3) ...........69 figure 6.16. 10-bit adc0 window interrupt exam ple: right justified single-ended data .70 figure 6.17. 10-bit adc0 window interrupt exam ple: right justified differential data.....71 figure 6.18. 10-bit adc0 window interrupt exam ple: left justified single-ended data....72 figure 6.19. 10-bit adc0 window interrupt exam ple: left justified differential data.......73 table 6.1. 10-bit adc0 electrical ch aracteristics (c8051f022/3).....................................74 7. adc1 (8-bit adc) ............................................................................................................. ..75 figure 7.1. adc1 functiona l block diagram .......................................................................75 figure 7.2. adc1 track and conve rsion example timing ..................................................77 figure 7.3. adc1 equivalent input circuit...........................................................................78 figure 7.4. adc1cf: adc1 configurat ion register (c8051f020/1/2/3)............................79 figure 7.5. amx1sl: amux1 channel sel ect register (c8 051f020/1/2/3) .....................79 figure 7.6. adc1cn: adc1 contro l register (c8051f020/1/2/3) .....................................80 figure 7.7. adc1: adc1 data word register .....................................................................81 figure 7.8. adc1 data word example.................................................................................81 table 7.1. adc1 electrical characteristics..........................................................................82 8. dacs, 12-bit voltage mode ......................................................................................83 figure 8.1. dac functional block diagram .........................................................................83 figure 8.2. dac0h: dac0 high byte register ...................................................................85 figure 8.3. dac0l: dac0 lo w byte register ....................................................................85 figure 8.4. dac0cn: dac0 control register .....................................................................86 figure 8.5. dac1h: dac1 high byte register ...................................................................87 figure 8.6. dac1l: dac1 lo w byte register ....................................................................87 figure 8.7. dac1cn: dac1 control register .....................................................................88 table 8.1. dac electrical characteristics............................................................................89 9. voltage referenc e (c8051f020/2)..........................................................................91
c8051f020/1/2/3 rev. 1.4 11 figure 9.1. voltage reference f unctional block diagram....................................................91 figure 9.2. ref0cn: referen ce control register ................................................................92 table 9.1. voltage reference elec trical characteristics ......................................................92 10. voltage referenc e (c8051f021/3)..........................................................................93 figure 10.1. voltage reference f unctional block diagram ...................................................93 figure 10.2. ref0cn: referenc e control register ................................................................94 table 10.1. voltage reference elec trical characteristics ......................................................94 11. comparators................................................................................................................. .95 figure 11.1. comparator functi onal block diagram ..............................................................95 figure 11.2. comparator hysteresis plot.................................................................................96 figure 11.3. cpt0cn: comparator0 control register ...........................................................97 figure 11.4. cpt1cn: comparator1 control register ...........................................................98 table 11.1. comparator electri cal characteristics.................................................................99 12. cip-51 microcon troller........................................................................................101 figure 12.1. cip-51 bloc k diagram ......................................................................................101 table 12.1. cip-51 instructio n set summary.......................................................................103 figure 12.2. memory map .....................................................................................................107 table 12.2. special function regist er (sfr) memory map................................................109 table 12.3. special functi on registers ................................................................................109 figure 12.3. sp: stack pointer ...............................................................................................11 3 figure 12.4. dpl: data pointer low byte ............................................................................113 figure 12.5. dph: data pointer high byte ...........................................................................113 figure 12.6. psw: program status word ..............................................................................114 figure 12.7. acc: accumulator............................................................................................115 figure 12.8. b: b register ..................................................................................................... 115 table 12.4. interrupt summary.............................................................................................117 figure 12.9. ie: interrupt enable ...........................................................................................119 figure 12.10. ip: interr upt priority ........................................................................................120 figure 12.11. eie1: extended in terrupt enable 1 .................................................................121 figure 12.12. eie2: extended in terrupt enable 2 .................................................................122 figure 12.13. eip1: extended in terrupt priority 1.................................................................123 figure 12.14. eip2: extended in terrupt priority 2.................................................................124 figure 12.15. pcon: po wer control.....................................................................................126 13. reset sources ..............................................................................................................1 27 figure 13.1. reset sources ....................................................................................................1 27 figure 13.2. reset timing .....................................................................................................1 28 figure 13.3. wdtcn: watchdog ti mer control register ...................................................131 figure 13.4. rstsrc: reset source register.......................................................................132 table 13.1. reset electrical characteristics .........................................................................133 14. oscillators................................................................................................................. ..135 figure 14.1. oscillator diagram ............................................................................................135 figure 14.2. oscicn: internal osci llator control register .................................................136 table 14.1. internal oscillator el ectrical characteristics.....................................................136 figure 14.3. oscxcn: external osci llator control re gister...............................................137 15. flash memory ..............................................................................................................13 9
c8051f020/1/2/3 12 rev. 1.4 table 15.1. flash electrical characteristics .....................................................................140 figure 15.1. flash program memory map and security bytes .........................................141 figure 15.2. flacl: flash access limit .........................................................................142 figure 15.3. flscl: flash memory control ....................................................................143 figure 15.4. psctl: program stor e read/write control .....................................................144 16. external data memory inter face and on-chip xram.......................145 figure 16.1. emi0cn: external memo ry interface control .................................................147 figure 16.2. emi0cf: external me mory configuration .......................................................147 figure 16.3. multiplexed conf iguration exam ple.................................................................148 figure 16.4. non-multiplexed c onfiguration ex ample .........................................................149 figure 16.5. emif oper ating modes.....................................................................................150 figure 16.6. emi0tc: external me mory timing control ....................................................152 figure 16.7. non-multiplexed 16-bit movx timing ...........................................................153 figure 16.8. non-multiplexed 8-bit movx without bank select timing............................154 figure 16.9. non-multiplexed 8-bit m ovx with bank select timing.................................155 figure 16.10. multiplexed 16- bit movx timing .................................................................156 figure 16.11. multiplexed 8-bit movx without bank select timing .................................157 figure 16.12. multiplexed 8-bit movx with bank select timing.......................................158 table 16.1. ac parameters for exte rnal memory interface.................................................159 17. port input/ou tput .....................................................................................................161 figure 17.1. port i/o cell block diagram.............................................................................161 table 17.1. port i/o dc electrical charac teristics ..............................................................161 figure 17.2. lower port i/o func tional block diagram .......................................................162 figure 17.3. priority crossb ar decode table ........................................................................163 figure 17.4. priority crossb ar decode table ........................................................................166 figure 17.5. priority crossb ar decode table ........................................................................167 figure 17.6. crossbar example: ............................................................................................169 figure 17.7. xbr0: port i/o cr ossbar regist er 0 .................................................................170 figure 17.8. xbr1: port i/o cr ossbar regist er 1 .................................................................171 figure 17.9. xbr2: port i/o cr ossbar regist er 2 .................................................................172 figure 17.10. p0: port0 data register ...................................................................................173 figure 17.11. p0mdout: port0 ou tput mode register.......................................................173 figure 17.12. p1: port1 data register ...................................................................................174 figure 17.13. p1mdin: port1 i nput mode register .............................................................174 figure 17.14. p1mdout: port1 ou tput mode register.......................................................175 figure 17.15. p2: port2 data register ...................................................................................175 figure 17.16. p2mdout: port2 ou tput mode register.......................................................175 figure 17.17. p3: port3 data register ...................................................................................176 figure 17.18. p3mdout: port3 ou tput mode register.......................................................176 figure 17.19. p3if: port3 inte rrupt flag register .................................................................177 figure 17.20. p74out: ports 7 - 4 output mode register ...................................................179 figure 17.21. p4: port4 data register ...................................................................................180 figure 17.22. p5: port5 data register ...................................................................................180 figure 17.23. p6: port6 data register ...................................................................................181 figure 17.24. p7: port7 data register ...................................................................................181
c8051f020/1/2/3 rev. 1.4 13 18. system managemen t bus / i2c bus (smbus0) .................................................183 figure 18.1. smbus0 block diagram ...................................................................................183 figure 18.2. typical smbus configuration ..........................................................................184 figure 18.3. smbus tran saction ...........................................................................................185 figure 18.4. typical master tr ansmitter seque nce...............................................................187 figure 18.5. typical master receiver sequ ence ...................................................................187 figure 18.6. typical slave tr ansmitter seque nce .................................................................188 figure 18.7. typical slave receiver sequence .....................................................................188 figure 18.8. smb0cn: smbus0 control register ...............................................................191 figure 18.9. smb0cr: smbus0 cl ock rate register ..........................................................192 figure 18.10. smb0dat: smbus0 data register ...............................................................193 figure 18.11. smb0adr: smbus0 address register..........................................................193 figure 18.12. smb0sta: smbus0 status regi ster..............................................................194 table 18.1. smb0sta status codes and states ..................................................................195 19. serial peripheral inter face bus (spi0) ........................................................197 figure 19.1. spi block diagram............................................................................................197 figure 19.2. typical spi interconnection ..............................................................................198 figure 19.3. full duplex operation. ......................................................................................199 figure 19.4. data/clock timing diagram .............................................................................200 figure 19.5. spi0cfg: spi0 conf iguration register............................................................201 figure 19.6. spi0cn: spi0 control register ........................................................................202 figure 19.7. spi0ckr: spi0 clock rate register ................................................................203 figure 19.8. spi0dat: spi0 data register ..........................................................................203 20. uart0 ....................................................................................................................... ...........205 figure 20.1. uart0 block diagram.....................................................................................205 table 20.1. uart0 m odes ..................................................................................................206 figure 20.2. uart0 mode 0 interconnect............................................................................206 figure 20.3. uart0 mode 0 timing diag ram .....................................................................206 figure 20.4. uart0 mode 1 timing diag ram .....................................................................207 figure 20.5. uart modes 2 and 3 timing diagram............................................................208 figure 20.6. uart modes 1, 2, and 3 interconnect diagram ..............................................209 figure 20.7. uart multi-processor mode interconnect diagram .......................................210 table 20.2. oscillator frequencies for standard baud rates...............................................212 figure 20.8. scon0: uart0 control register....................................................................213 figure 20.9. sbuf0: uart0 data buffer register..............................................................214 figure 20.10. saddr0: uart0 sl ave address register ....................................................214 figure 20.11. saden0: uart0 slave address enable register ........................................214 21. uart1 ....................................................................................................................... ...........215 figure 21.1. uart1 block diagram.....................................................................................215 table 21.1. uart1 m odes ..................................................................................................216 figure 21.2. uart1 mode 0 interconnect............................................................................216 figure 21.3. uart1 mode 0 timing diag ram .....................................................................216 figure 21.4. uart1 mode 1 timing diag ram .....................................................................217 figure 21.5. uart modes 2 and 3 timing diagram............................................................218 figure 21.6. uart modes 1, 2, and 3 interconnect diagram ..............................................219
c8051f020/1/2/3 14 rev. 1.4 figure 21.7. uart multi-processor mode interconnect diagram .......................................220 table 21.2. oscillator frequencies for standard baud rates...............................................222 figure 21.8. scon1: uart1 control register....................................................................223 figure 21.9. sbuf1: uart1 data buffer register..............................................................224 figure 21.10. saddr1: uart1 sl ave address register ....................................................224 figure 21.11. saden1: uart1 slave address enable register ........................................224 22. timers...................................................................................................................... ..........225 figure 22.1. ckcon: clock control register......................................................................226 figure 22.2. t0 mode 0 block diagram................................................................................228 figure 22.3. t0 mode 2 (8-bit auto-reload) block diagram...............................................229 figure 22.4. t0 mode 3 (two 8-bi t timers) block diagram................................................230 figure 22.5. tcon: timer c ontrol register.........................................................................231 figure 22.6. tmod: timer mode register...........................................................................232 figure 22.7. tl0: timer 0 low byte ....................................................................................233 figure 22.8. tl1: timer 1 low byte ....................................................................................233 figure 22.9. th0 timer 0 high byte ....................................................................................233 figure 22.10. th1: time r 1 high byte .................................................................................233 figure 22.11. t2 mode 0 block diagram..............................................................................235 figure 22.12. t2 mode 1 block diagram..............................................................................236 figure 22.13. t2 mode 2 block diagram..............................................................................237 figure 22.14. t2con: timer 2 control regi ster..................................................................238 figure 22.15. rcap2l: timer 2 ca pture register low byte ..............................................239 figure 22.16. rcap2h: timer 2 ca pture register high byte .............................................239 figure 22.17. tl2: time r 2 low byte ..................................................................................239 figure 22.18. th2 time r 2 high byte ..................................................................................239 figure 22.19. timer 3 bl ock diagram...................................................................................240 figure 22.20. tmr3cn: timer 3 control register ..............................................................241 figure 22.21. tmr3rll: timer 3 re load register low byte ............................................241 figure 22.22. tmr3rlh: timer 3 re load register high byte ...........................................242 figure 22.23. tmr3l: ti mer 3 low byte ............................................................................242 figure 22.24. tmr3h: ti mer 3 high byte ...........................................................................242 figure 22.25. t4 mode 0 block diagram..............................................................................244 figure 22.26. t4 mode 1 block diagram..............................................................................245 figure 22.27. t4 mode 2 block diagram..............................................................................246 figure 22.28. t4con: timer 4 control regi ster..................................................................247 figure 22.29. rcap4l: timer 4 ca pture register low byte ..............................................248 figure 22.30. rcap4h: timer 4 ca pture register high byte .............................................248 figure 22.31. tl4: time r 4 low byte ..................................................................................248 figure 22.32. th4 time r 4 high byte ..................................................................................248 23. programmable co unter array .......................................................................249 figure 23.1. pca block diagram..........................................................................................249 figure 23.2. pca counter/timer block diagram .................................................................250 table 23.1. pca timebase input options............................................................................250 figure 23.3. pca interrupt block diagram...........................................................................252 table 23.2. pca0cpm register settings for pca capture/compare modules..................252
c8051f020/1/2/3 rev. 1.4 15 figure 23.4. pca capture mode diagram ............................................................................253 figure 23.5. pca software timer mode diagram................................................................254 figure 23.6. pca high speed output mode diagram ..........................................................255 figure 23.7. pca frequency output mode ...........................................................................256 figure 23.8. pca 8-bit pwm mode diagram ......................................................................257 figure 23.9. pca 16-bit pwm mode ...................................................................................258 figure 23.10. pca0cn: pca control register ....................................................................259 figure 23.11. pca0md: pca0 mode register ....................................................................260 figure 23.12. pca0cpmn: pca0 captur e/compare mode registers .................................261 figure 23.13. pca0l: pca0 c ounter/timer low byte .......................................................262 figure 23.14. pca0h: pca0 c ounter/timer high byte ......................................................262 figure 23.15. pca0cpln: pca0 capture module low byte ..............................................263 figure 23.16. pca0cphn: pca0 capture module high byte .............................................263 24. jtag (ieee 1149.1).......................................................................................................... ..265 figure 24.1. ir: jtag instruction register ..........................................................................265 table 24.1. boundary data regist er bit defin itions............................................................266 figure 24.2. deviceid: jtag de vice id regi ster ............................................................267 figure 24.3. flashcon: jtag fl ash control register.....................................................269 figure 24.4. flashadr: jtag fl ash address register ....................................................270 figure 24.5. flashdat: jtag flash data register..........................................................270
c8051f020/1/2/3 16 rev. 1.4 notes
c8051f020/1/2/3 rev. 1.4 17 1. system overview the c8051f020/1/2/3 devices are fully integrated mixed-sign al system-on-a-chip mcus with 64 digital i/o pins (c8051f020/2) or 32 digital i/o pins (c8051f021/3). highlighted features are listed below; refer to table 1.1 for specific product feature selection. ? high-speed pipelined 8051-compatible cip-51 microcontroller core (up to 25 mips) ? in-system, full-speed, non-intrusive debug interface (on-chip) ? true 12-bit (c8051f020/1) or 10-bit (c8051f022/3) 100 ksps 8-channel adc with pga and analog multiplexer ? true 8-bit adc 500 ksps 8-channel adc with pga and analog multiplexer ? two 12-bit dacs with programmable update scheduling ? 64k bytes of in-system programmable flash memory ? 4352 (4096 + 256) bytes of on-chip ram ? external data memory interf ace with 64k byte address space ?spi, smbus/i 2 c, and (2) uart serial interfaces implemented in hardware ? five general purpose 16-bit timers ? programmable counter/timer array with five capture/compare modules ? on-chip watchdog timer, vdd monitor, and temperature sensor with on-chip vdd monitor, watchdog timer, and clock oscillator, the c8051f020/1/2/3 devices are truly stand- alone system-on-a-chip solutions. all analog and digital peripherals are enabled/disabled an d configured by user firmware. the flash memory can be reprogrammed even in -circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. on-board jtag debug circuitry allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production mcu installed in the final application. this debug system supports inspection and modification of memory and registers, setting breakpoints, watchpoints, single stepping, run and halt commands. all analog and digital peripherals are fully functional while debugging using jtag. each mcu is specified for 2.7 v-to-3.6 v operation over the industri al temperature range (-45 c to +85 c). the port i/os, /rst, and jtag pins are tolerant for input signals up to 5 v. the c8051f020/2 are available in a 100-pin tqfp package (see block diagrams in figure 1.1 and figure 1.3 ). the c8051f021/3 are available in a 64-pin tqfp package (see block diagrams in figure 1.2 and figure 1.4 ). table 1.1. product selection guide mips (peak) flash memory ram external memory interface smbus/i 2 c spi uarts timers (16-bit) programmable counter array digital port i/o?s 12-bit 100ksps adc inputs 10-bit 100ksps adc inputs 8-bit 500ksps adc inputs voltage reference temperature sensor dac resolution (bits) dac outputs analog comparators package c8051f020 25 64k 4352 3 3 3 2 5 3 64 8 - 8 3 3 12 2 2 100tqfp c8051f021 25 64k 4352 3 3 3 2 5 3 32 8 - 8 3 3 12 2 2 64tqfp c8051f022 25 64k 4352 3 3 3 2 5 3 64 - 8 8 3 3 12 2 2 100tqfp C8051F023 25 64k 4352 3 3 3 2 5 3 32 - 8 8 3 3 12 2 2 64tqfp
c8051f020/1/2/3 18 rev. 1.4 figure 1.1. c8051f020 block diagram p0, p1, p2, p3 latches jtag logic tck tms tdi tdo uart1 smbus spi bus pca 64kbyte flash 256 byte ram vdd monitor sfr bus 8 0 5 1 c o r e timers 0, 1, 2, 4 timer 3/ rtc p0 drv c r o s s b a r port i/o config. crossbar config. av+ av+ vdd vdd vdd dgnd dgnd dgnd agnd agnd reset /rst xtal1 xtal2 external oscillator circuit system clock internal oscillator digital power analog power debug hw boundary scan 4kbyte ram p2.0 p2.7 p1.0/ain1.0 p1.7/ain1.7 p0.0 p0.7 p1 drv p2 drv data bus address bus bus control dac1 dac1 (12-bit) vref dac0 (12-bit) adc 100ksps (12-bit) a m u x ain0.0 ain0.1 ain0.2 ain0.3 ain0.4 ain0.5 ain0.6 ain0.7 dac0 cp0+ cp0- cp1+ cp1- vref temp sensor uart0 p3.0 p3.7 p3 drv 8:1 monen wdt vrefd vref0 prog gain cp0 cp1 c t l p4 latch d a t a p7 latch a d d r p5 latch p6 latch p7.0/d0 p7.7/d7 p7 drv p5.0/a8 p5.7/a15 p5 drv p6.0/a0 p6.7/a7 p6 drv p4 drv p4.5/ale p4.6/rd p4.7/wr p4.0 p4.4 external data memory bus prog gain adc 500ksps (8-bit) a m u x vref1
c8051f020/1/2/3 rev. 1.4 19 figure 1.2. c8051f021 block diagram p0, p1, p2, p3 latches jtag logic tck tms tdi tdo uart1 smbus spi bus pca 64kbyte flash 256 byte ram vdd monitor sfr bus 8 0 5 1 c o r e timers 0, 1, 2, 4 timer 3/ rtc p0 drv c r o s s b a r port i/o config. crossbar config. av+ vdd vdd vdd dgnd dgnd dgnd agnd reset /rst xtal1 xtal2 external oscillator circuit system clock internal oscillator digital power analog power debug hw boundary scan 4kbyte ram p2.0 p2.7 p1.0/ain1.0 p1.7/ain1.7 p0.0 p0.7 p1 drv p2 drv data bus address bus bus control dac1 dac1 (12-bit) vref dac0 (12-bit) adc 100ksps (12-bit) a m u x ain0.0 ain0.1 ain0.2 ain0.3 ain0.4 ain0.5 ain0.6 ain0.7 dac0 cp0+ cp0- cp1+ cp1- vref temp sensor uart0 p3.0 p3.7 p3 drv 8:1 monen wdt vrefa prog gain cp0 cp1 c t l p4 latch d a t a p7 latch a d d r p5 latch p6 latch p7 drv p5 drv p6 drv p4 drv external data memory bus prog gain adc 500ksps (8-bit) a m u x vrefa av+
c8051f020/1/2/3 20 rev. 1.4 p0, p1, p2, p3 latches jtag logic tck tms tdi tdo uart1 smbus spi bus pca 64kbyte flash 256 byte ram vdd monitor sfr bus 8 0 5 1 c o r e timers 0, 1, 2, 4 timer 3/ rtc p0 drv c r o s s b a r port i/o config. crossbar config. av+ av+ vdd vdd vdd dgnd dgnd dgnd agnd agnd reset /rst xtal1 xtal2 external oscillator circuit system clock internal oscillator digital power analog power debug hw boundary scan 4kbyte ram p2.0 p2.7 p1.0/ain1.0 p1.7/ain1.7 p0.0 p0.7 p1 drv p2 drv data bus address bus bus control dac1 dac1 (12-bit) vref dac0 (12-bit) adc 100ksps (10-bit) a m u x ain0.0 ain0.1 ain0.2 ain0.3 ain0.4 ain0.5 ain0.6 ain0.7 dac0 cp0+ cp0- cp1+ cp1- vref temp sensor uart0 p3.0 p3.7 p3 drv 8:1 monen wdt vrefd vref0 prog gain cp0 cp1 c t l p4 latch d a t a p7 latch a d d r p5 latch p6 latch p7.0/d0 p7.7/d7 p7 drv p5.0/a8 p5.7/a15 p5 drv p6.0/a0 p6.7/a7 p6 drv p4 drv p4.5/ale p4.6/rd p4.7/wr p4.0 p4.4 external data memory bus prog gain adc 500ksps (8-bit) a m u x vref1 figure 1.3. c8051f022 block diagram
c8051f020/1/2/3 rev. 1.4 21 p0, p1, p2, p3 latches jtag logic tck tms tdi tdo uart1 smbus spi bus pca 64kbyte flash 256 byte ram vdd monitor sfr bus 8 0 5 1 c o r e timers 0, 1, 2, 4 timer 3/ rtc p0 drv c r o s s b a r port i/o config. crossbar config. av+ vdd vdd vdd dgnd dgnd dgnd agnd reset /rst xtal1 xtal2 external oscillator circuit system clock internal oscillator digital power analog power debug hw boundary scan 4kbyte ram p2.0 p2.7 p1.0/ain1.0 p1.7/ain1.7 p0.0 p0.7 p1 drv p2 drv data bus address bus bus control dac1 dac1 (12-bit) vref dac0 (12-bit) adc 100ksps (10-bit) a m u x ain0.0 ain0.1 ain0.2 ain0.3 ain0.4 ain0.5 ain0.6 ain0.7 dac0 cp0+ cp0- cp1+ cp1- vref temp sensor uart0 p3.0 p3.7 p3 drv 8:1 monen wdt vrefa prog gain cp0 cp1 c t l p4 latch d a t a p7 latch a d d r p5 latch p6 latch p7 drv p5 drv p6 drv p4 drv external data memory bus prog gain adc 500ksps (8-bit) a m u x vrefa av+ figure 1.4. C8051F023 block diagram
c8051f020/1/2/3 22 rev. 1.4 1.1. cip-51? microcontroller core 1.1.1. fully 8051 compatible the c8051f020 family utilizes silicon labs' proprietary cip-51 microcontroller core. th e cip-51 is fully compati - ble with the mcs-51? instruction set; standard 803x/805x assemblers and compilers can be used to develop soft - ware. the core has all the peripherals included with a standard 8052, including five 16-bit counter/timers, two full- duplex uarts, 256 bytes of internal ram, 128 byte special function register (sfr) address space, and 8/4 byte- wide i/o ports. 1.1.2. improved throughput the cip-51 employs a pipelined architectur e that greatly increases its instruct ion throughput over the standard 8051 architecture. in a standard 8051, all instru ctions except for mul and div take 12 or 24 system clock cycles to exe - cute with a maximum sy stem clock of 12-to-24 mhz. by contrast, the ci p-51 core executes 70% of its instructions in one or two system clock cycles, with only four instru ctions taking more than four system clock cycles. the cip-51 has a total of 109 instructions. the table below shows the total number of instructi ons that require each execution time. with the cip-51's maxi mum system clock at 25 mhz, it has a peak throughput of 25 mips. figure 1.5 shows a com - parison of peak throughputs of various 8-bit microc ontroller cores with their maximum system clocks. clocks to execute 1 2 2/3 3 3/4 4 4/5 5 8 number of instructions 26 50 5 14 7 3 1 2 1 5 10 15 20 aduc812 8051 (16mhz clk) philips 80c51 (33mhz clk) microchip pic17c75x (33mhz clk) silicon labs cip-51 (25mhz clk) mips 25 figure 1.5. comparison of peak mcu execution speeds
c8051f020/1/2/3 rev. 1.4 23 1.1.3. additional features the c8051f020 mcu family includes several key enhancemen ts to the cip-51 core and peripherals to improve over - all performance and ease of use in end applications. the extended interrupt handler provides 22 interrupt sources into the cip-51 (as opposed to 7 for the standard 8051), allowing the numerous analog and digital peripherals to inte rrupt the controller. an interrupt driven system requires less intervention by the mcu, giving it more effective throughput. the extra interrupt sources are very useful when building multi-tasking, real-time systems. there are up to seven reset sources for the mcu: an on-board vdd monitor, a watch dog timer, a missing clock detector, a voltage level detection from comparator0, a for ced software reset, the cnvstr input pin, and the /rst pin. the /rst pin is bi-directional, acco mmodating an external reset, or allowi ng the internally generated por to be output on the /rst pin. each reset source except for the vd d monitor and reset input pin may be disabled by the user in software; the vdd monitor is enabled/disabled via the monen pin. the watchdog timer may be perma - nently enabled in software after a power-on reset during mcu initialization. the mcu has an internal, stand alone clock generator which is used by default as the system clock after any reset. if desired, the clock source may be switched on the fly to the external oscillator, which can use a crystal, ceramic reso - nator, capacitor, rc, or external clock source to generate th e system clock. this can be extremely useful in low power applications, allowing the mcu to run from a slow (power saving) external crystal sour ce, while periodically switch - ing to the fast (up to 16 mhz) internal oscillator as needed. wdt xtal1 xtal2 osc internal clock generator system clock cip-51 microcontroller core missing clock detector (one- shot) wdt strobe software reset extended interrupt handler clock select /rst + - vdd supply reset timeout (wired-or) system reset supply monitor pre reset funnel + - cp0+ comparator0 cp0- (port i/o) crossbar cnvstr (cnvstr reset enable) (cp0 reset enable) en wdt enable en mcd enable figure 1.6. on-board clock and reset
c8051f020/1/2/3 24 rev. 1.4 1.2. on-chip memory the cip-51 has a standard 8051 program and data address configuration. it includes 256 bytes of data ram, with the upper 128 bytes dual-mapped. indirect addressing accesses the upper 128 bytes of general purpose ram, and direct addressing accesses the 128 byte sfr address space. the lower 128 bytes of ram are accessible via direct and indi - rect addressing. the first 32 bytes are addressable as four banks of general purpose registers, and the next 16 bytes can be byte addressable or bit addressable. the cip-51 in the c8051f020/1/2/3 mcus additionally has an on-chip 4k byte ram block and an external memory interface (emif) for accessing off-ch ip data memory. the on-chip 4k byte block can be addressed over the entire 64k external data memory address range (overlapping 4k boundaries ). external data memory address space can be mapped to on-chip memory only, off-chip memory only, or a combination of the two (addresses up to 4k directed to on-chip, above 4k directed to emif). th e emif is also configurable for multiplexed or non-multiplexed address/data lines. the mcu?s program memory consists of 64k bytes of flash. this memory may be reprogrammed in-system in 512 byte sectors, and requires no special off-chip programming voltage. the 512 bytes from addresses 0xfe00 to 0xffff are reserved for factory use. there is also a single 128 byte sector at address 0x10000 to 0x1007f, which may be useful as a small table for software constants. see figure 1.7 for the mcu system memory map. program/data memory (flash) (direct and indirect addressing) 0x00 0x7f upper 128 ram (indirect addressing only) 0x80 0xff special function register's (direct addressing only) data memory (ram) general purpose registers 0x1f 0x20 0x2f bit addressable lower 128 ram (direct and indirect addressing) 0x30 internal data address space external data address space xram - 4096 bytes (accessable using movx instruction) 0x0000 0x0fff off-chip xram space 0x1000 0xffff flash (in-system programmable in 512 byte sectors) 0x0000 0xffff reserved 0xfe00 0xfdff scrachpad memory (data only) 0x1007f 0x10000 figure 1.7. on-chip memory map
c8051f020/1/2/3 rev. 1.4 25 1.3. jtag debug and boundary scan the c8051f020 family has on-chip jtag bounda ry scan and debug circuitry that provides non-intrusive, full speed, in-circuit debugging using the production part installed in the end application , via the four-pin jtag interface. the jtag port is fully compliant to ieee 1149.1, providing full boundary scan for test and manufacturing purposes. silicon labs' debugging system supports inspection and m odification of memory and registers, breakpoints, watch - points, a stack monitor, and single stepping. no additiona l target ram, program memory, timers, or communications channels are required. all the digital and analog peripherals are functional an d work correctly while debugging. all the peripherals (except for the adc and smbus) are stalled when the mcu is halted, during single stepping, or at a breakpoint in order to keep them synchronized. the c8051f020dk development kit provides all the hardware and software necessary to develop application code and perform in-circuit debugging with the c8051f020/1/2/3 mc us. the kit includes software with a developer's stu - dio and debugger, an integrated 8051 assembler, and an rs-232 to jtag serial adapter. it also has a target application board with the associated mcu instal led, plus the rs-232 and jtag cables, and wall-mount power supply. the development kit requires a windows 95/98/nt/me/2000 com puter with one available rs-232 serial port. as shown in figure 1.8 , the pc is connected via rs-232 to the serial adapter. a six-inch ribbon cable connects the serial adapter to the user's application board, picking up the f our jtag pins and vdd and gnd. the serial adapter takes its power from the application board; it requires roughly 20 ma at 2.7-3.6 v. for applications wh ere there is not suf - ficient power available fr om the target system, the provided power supp ly can be connected di rectly to the serial adapter. silicon labs? debug environment is a vastly superior co nfiguration for developing and debugging embedded applica - tions compared to standard mcu emulat ors, which use on-board "ice chips" and target cables and require the mcu in the application board to be socketed. silicon labs' debu g environment both increases ease of use and preserves the performance of the precision analog peripherals. target pcb rs-232 serial adapter c8051 f020 vdd gnd jtag (x4), vdd, gnd windows 95/98/nt/me/2000 silicon labs integrated development environment figure 1.8. development/in-system debug diagram
c8051f020/1/2/3 26 rev. 1.4 1.4. programmable digital i/o and crossbar the standard 8051 ports (0, 1, 2, and 3) are available on the mcus. the c8051f020/2 have 4 additional ports (4, 5, 6, and 7) for a total of 64 general-pur pose port i/o. the port i/o behave like the standard 8051 with a few enhance - ments. each port i/o pin can be configured as either a push-pull or open-drain output. also, the "weak pull-ups" which are normally fixed on an 8051 can be globally disabled, pr oviding additional power saving capabilities for low-power applications. perhaps the most unique enhancement is the digital crossbar. this is essentially a large digital switching network that allows mapping of internal digital system resources to port i/o pins on p0, p1, p2, and p3. (see figure 1.9 ) unlike microcontrollers with standard multiplexed digi tal i/o, all combinations of functions are supported. the on-chip counter/timers, serial buses, hw interrupts, adc start of conversion input, comparator outputs, and other digital signals in the controller can be configured to appear on the port i/o pins sp ecified in the crossbar con - trol registers. this allows the user to select the exact mix of general purpose port i/o and digital resources needed for the particular application. external pins digital crossbar priority decoder smbus 2 spi 4 uart0 2 pca 2 t0, t1, t2, t2ex, t4,t4ex /int0, /int1 p1.0 p1.7 p2.0 p2.7 p0.0 p0.7 highest priority lowest priority 8 8 comptr. outputs (internal digital signals) highest priority lowest priority uart1 /sysclk cnvstr 6 2 p3.0 p3.7 8 8 p0mdout, p1mdout, p2mdout, p3mdout registers xbr0, xbr1, xbr2, p1mdin registers p1 i/o cells p3 i/o cells p0 i/o cells p2 i/o cells 8 port latches p0 p1 p2 8 8 8 p3 8 (p2.0-p2.7) (p1.0-p1.7) (p0.0-p0.7) (p3.0-p3.7) to adc1 input to external memory interface (emif) figure 1.9. digital crossbar diagram
c8051f020/1/2/3 rev. 1.4 27 1.5. programmable counter array the c8051f020 mcu family includes an on-board programma ble counter/timer array (pca) in addition to the five 16-bit general purpose counter/timers. th e pca consists of a dedicated 16-bit counter/timer time base with 5 pro - grammable capture/compare modules. the timebase is clocke d from one of six sources: the system clock divided by 12, the system clock divided by 4, timer 0 overflow, an ex ternal clock input (eci pin), the system clock, or the external oscillator source divided by 8. each capture/compare module can be conf igured to operate in one of six modes: edge-triggered capture, software timer, high speed output, frequency output, 8-bit pulse width modulator, or 16-bit pulse width modulator. the pca capture/compare module i/o and external clock input are routed to the mcu port i/o via the digital cross - bar. 1.6. serial ports the c8051f020 mcu family includes two enhanced full-duplex uarts, spi bus, and smbus/i 2 c. each of the serial buses is fully implemented in hardware and makes ex tensive use of the cip-51's inte rrupts, thus requiring very little intervention by the cpu. the serial buses do not "share" resources such as timers, inte rrupts, or port i/o, so any or all of the serial buses may be used together with any other. capture/compare module 1 capture/compare module 0 capture/compare module 2 capture/compare module 3 capture/compare module 4 cex1 eci crossbar cex2 cex3 cex4 cex0 port i/o 16-bit counter/timer pca clock mux sysclk/12 sysclk/4 timer 0 overflow eci sysclk external clock/8 figure 1.10. pca block diagram
c8051f020/1/2/3 28 rev. 1.4 1.7. 12-bit analog to digital converter the c8051f020/1 has an on-chip 12-bit sar adc (adc0) with a 9-channel input multiplexer and programmable gain amplifier. with a maximum throughput of 100 ksps, the adc offers true 12-bit accuracy with an inl of 1lsb. c8051f022/3 devices include a 10-bit sar adc with similar specifications and configuration options. the adc0 voltage reference is selected between the dac0 output and an external vref pin. on c8051f020/2 devices, adc0 has its own dedicated vref0 input pin; on c8051f021/3 devices, the adc0 shares the vrefa input pin with the 8- bit adc1. the on-chip 15 ppm/c voltage reference may generate the voltage reference for other system components or the on-chip adcs via the vref output pin. the adc is under full control of the cip-51 microcontroller via its associated special function registers. one input channel is tied to an internal temperat ure sensor, while the other eight channels are available externally. each pair of the eight external input channe ls can be configured as either two single-e nded inputs or a single differential input. the system controller can also put the adc into shutdown mode to save power. a programmable gain amplifier follows the analog multiplexer. the gain can be set in software from 0.5 to 16 in powers of 2. the gain stage can be esp ecially useful when differ ent adc input channels have widely varied input voltage signals, or when it is necessary to "zoom in" on a signal with a large dc offset (in differential mode, a dac could be used to provide the dc offset). conversions can be started in four ways; a software command, an overflow of timer 2, an overflow of timer 3, or an external signal input. this flexibility allows the start of c onversion to be triggered by software events, external hw signals, or a periodic timer overflow signal. conversion comp letions are indicated by a stat us bit and an interrupt (if enabled). the resulting 10 or 12-bit data word is latched into two sfrs upon completion of a conversion. the data can be right or left justified in these registers under software control. window compare registers for the adc data can be configured to interrupt the controller when adc data is within or outside of a specified range. the adc can monitor a key voltage continuously in background mode, but not inter - rupt the controller unless the converted data is within the specified window. 12-bit sar adc 12 + - temp sensor + - + - + - 9-to-1 amux (se or diff) + - x ain0.0 ain0.1 ain0.2 ain0.3 ain0.4 ain0.5 ain0.6 ain0.7 av+ programmable gain amplifier analog multiplexer window compare logic adc data registers window compare interrupt conversion complete interrupt configuration, control, and data registers start conversion timer 3 overflow timer 2 overflow write to ad0busy cnvstr external vref pin dac0 output vref agnd figure 1.11. 12-bit adc block diagram
c8051f020/1/2/3 rev. 1.4 29 1.8. 8-bit analog to digital converter the c8051f020/1/2/3 has an on-board 8-bit sar adc (adc1) with an 8-channel input multiplexer and programma - ble gain amplifier. this adc features a 500 ksps maximum throughput and true 8-bit accuracy with an inl of 1lsb. eight input pins are available for measurement. the adc is under full control of the cip-51 microcontroller via the special function registers. the adc1 voltage refe rence is selected between the analog power supply (av+) and an external vref pin. on c8051f020/2 devices, adc1 has its own dedicated vref1 input pin; on c8051f021/3 devices, adc1 shares the vrefa input pin with the 12/10-bit adc0. user software may put adc1 into shutdown mode to save power. a programmable gain amplifier follows the analog multiplexer . the gain stage can be esp ecially useful when differ - ent adc input channels have widely varied input voltage si gnals, or when it is necessary to "zoom in" on a signal with a large dc offset (in differential mode, a dac could be used to provide the dc offset). the pga gain can be set in software to 0.5, 1, 2, or 4. a flexible conversion scheduling system allows adc1 conversions to be initiated by software commands, timer overflows, or an external input signal. adc1 conversions may also be synchronized with adc0 software-com - manded conversions. conversion completions are indicated by a status bit and an interrupt (if enabled), and the resulting 8-bit data word is latched into an sfr upon completion. + - av+ 8 8-to-1 amux x ain1.0 ain1.1 ain1.2 ain1.3 ain1.4 ain1.5 ain1.6 ain1.7 configuration, control, and data registers programmable gain amplifier analog multiplexer 8-bit sar adc start conversion timer 3 overflow timer 2 overflow write to ad1busy cnvstr input write to ad0busy (synchronized with adc0) adc data register conversion complete interrupt external vref pin av+ vref figure 1.12. 8-bi t adc diagram
c8051f020/1/2/3 30 rev. 1.4 1.9. comparators and dacs each c8051f020/1/2/3 mcu has two 12-bit dacs and two comparators on chip. the mcu data and control inter - face to each comparator and dac is vi a the special function registers. the mcu can place any dac or comparator in low power shutdown mode. the comparators have so ftware programmable hysteresis . each comparator can genera te an interrupt on its rising edge, falling edge, or both; these inte rrupts are capable of waking up the mc u from sleep mode. the comparators' output state can also be polled in software. the comparator outputs can be programmed to appear on the port i/o pins via the crossbar. the dacs are voltage output mode, and include a flexible output scheduling mechanism. this scheduling mecha - nism allows dac output updates to be forced by a software write or a timer 2, 3, or 4 overflow. the dac voltage reference is supplied via the dedicated vrefd input pin on c8051f020/2 devices or via the internal voltage refer - ence on c8051f021/3 devices. the dacs are especially useful as references fo r the comparators or offsets for the differential inputs of the adc. + - cp1 cp1+ cp1- dac0 dac1 ref ref cp0 cip-51 and interrupt handler cp1 dac0 dac1 cp0+ cp0- cp1 cp0 (port i/o) (port i/o) + - cp0 sfr's (data and cntrl) crossbar figure 1.13. comparator and dac diagram
c8051f020/1/2/3 rev. 1.4 31 2. absolute maximum ratings table 2.1. absolute maximum ratings * parameter conditions min typ max units ambient temperature under bias -55 125 c storage temperature -65 150 c voltage on any pin (except vdd and port i/o) with respect to dgnd -0.3 vdd + 0.3 v voltage on any port i/o pin or /rst with respect to dgnd -0.3 5.8 v voltage on vdd with re spect to dgnd -0.3 4.2 v maximum total current through vdd, av+, dgnd, and agnd 800 ma maximum output current sunk by any port pin 100 ma maximum output current sunk by any other i/o pin 50 ma maximum output current sourced by any port pin 100 ma maximum output current sourced by any other i/o pin 50 ma * stresses above those listed under ?absolute maximum ra tings? may cause permanent damage to the device. this is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not im plied. exposure to maximum rating conditions for extended periods may affect device reliability.
c8051f020/1/2/3 32 rev. 1.4 3. global dc electrical characteristics table 1.1. global dc electric al characteristics -40c to +85c, 25 mhz system clock unless otherwise specified. parameter conditions min typ max units analog supply voltage 2.7 ? 3.0 3.6 v analog supply current av+=2.7 v, internal ref, adc, dac, comparators all active 1.7 ma analog supply current with analog sub-systems inactive av+=2.7 v, internal ref, adc, dac, comparators all disabled, oscillator disabled, vdd monitor disabled 0.2 a analog-to-digital supply delta (|vdd - av+|) 0.5 v digital supply voltage 2.7 3.0 3.6 v digital supply current with cpu active vdd=2.7 v, clock=25 mhz vdd=2.7 v, clock=1 mhz vdd=2.7 v, clock=32 khz 10 0.5 20 ma ma a digital supply current with cpu inactive (not accessing flash) vdd=2.7 v, clock=25 mhz vdd=2.7 v, clock=1 mhz vdd=2.7 v, clock=32 khz 5 0.2 10 ma ma a digital supply current (shut- down) vdd=2.7 v, oscillator not running, vdd monitor disabled 0.2 a digital supply ram data retention voltage 1.5 v specified operating tempera- ture range -40 +85 c sysclk (system clock fre- quency) 0 ? 25 mhz tsysl (sysclk low time) 18 ns tsysh (sysclk high time) 18 ns ? analog supply av+ must be greater than 1 v for vdd mo nitor to operate. ? sysclk must be at least 32 khz to enable debugging.
c8051f020/1/2/3 rev. 1.4 33 4. pinout and pack age definitions table 4.1. pin definitions name pin numbers type description f020 f021 f022 f023 vdd 37, 64, 90 24, 41, 57 digital supply voltage. must be tied to +2.7 to +3.6 v. dgnd 38, 63, 89 25, 40, 56 digital ground. must be tied to ground. av + 11, 14 6 analog supply voltage. must be tied to +2.7 to +3.6 v. agnd 10, 13 5 analog ground. must be tied to ground. tms 1 58 d in jtag test mode select with internal pull-up. tck 2 59 d in jtag test clock with internal pull-up. tdi 3 60 d in jtag test data input with internal pull-up. tdi is latched on the rising edge of tck. tdo 4 61 d out jtag test data output with internal pull-up. data is shifted out on tdo on the falling edge of tck. tdo output is a tri-state driver. /rst 5 62 d i/o device reset. open-drain output of internal vdd monitor. is driven low when vdd is <2.7 v and monen is high. an external source can initiate a system reset by driving this pin low. xtal1 26 17 a in crystal input. this pin is the return for the internal oscillator circuit for a crystal or ceramic resonator. for a precision internal clock, connect a crystal or ceramic res onator from xtal1 to xtal2. if overdriven by an exte rnal cmos clock, this becomes the system clock. xtal2 27 18 a out crystal output. this pin is the excitation driver for a crystal or ceramic resonator. monen 28 19 d in vdd monitor enable. when tied high, this pin enables the internal vdd monitor, which forces a system reset when vdd is < 2.7 v. when tied low, the internal vdd monitor is disabled. vref 12 7 a i/o bandgap voltage reference output (all devices). dac voltage reference input (f021/3 only). vrefa 8 a in adc0 and adc1 voltage reference input. vref0 16 a in adc0 voltage reference input. vref1 17 a in adc1 voltage reference input. vrefd 15 a in dac voltage reference input.
c8051f020/1/2/3 34 rev. 1.4 ain0.0 18 9 a in adc0 input channel 0 (see adc0 specification for complete description). ain0.1 19 10 a in adc0 input channel 1 (see adc0 specification for complete description). ain0.2 20 11 a in adc0 input channel 2 (see adc0 specification for complete description). ain0.3 21 12 a in adc0 input channel 3 (see adc0 specification for complete description). ain0.4 22 13 a in adc0 input channel 4 (see adc0 specification for complete description). ain0.5 23 14 a in adc0 input channel 5 (see adc0 specification for complete description). ain0.6 24 15 a in adc0 input channel 6 (see adc0 specification for complete description). ain0.7 25 16 a in adc0 input channel 7 (see adc0 specification for complete description). cp0+ 9 4 a in comparator 0 non-inverting input. cp0- 8 3 a in comparator 0 inverting input. cp1+ 7 2 a in comparator 1 non-inverting input. cp1- 6 1 a in comparator 1 inverting input. dac0 100 64 a out digital to analog converter 0 voltage output. (see dac specifica - tion for complete description). dac1 99 63 a out digital to analog converter 1 voltage output. (see dac specifica - tion for complete description). p0.0 62 55 d i/o port 0.0. see port input/output section for complete description. p0.1 61 54 d i/o port 0.1. see port input/output section for complete description. p0.2 60 53 d i/o port 0.2. see port input/output section for complete description. p0.3 59 52 d i/o port 0.3. see port input/output section for complete description. p0.4 58 51 d i/o port 0.4. see port input/output section for complete description. ale/p0.5 57 50 d i/o ale strobe for external memory address bus (multiplexed mode) port 0.5 see port input/output section for complete description. table 4.1. pin definitions name pin numbers type description f020 f021 f022 f023
c8051f020/1/2/3 rev. 1.4 35 /rd/p0.6 56 49 d i/o /rd strobe for external memory address bus port 0.6 see port input/output section for complete description. /wr/p0.7 55 48 d i/o /wr strobe for external memory address bus port 0.7 see port input/output section for complete description. ain1.0/a8/p1.0 36 29 a in d i/o adc1 input channel 0 (see adc1 specification for complete description). bit 8 external memory address bus (non-multiplexed mode) port 1.0 see port input/output section for complete description. ain1.1/a9/p1.1 35 28 a in d i/o port 1.1. see port input/output section for complete description. ain1.2/a10/p1.2 34 27 a in d i/o port 1.2. see port input/output section for complete description. ain1.3/a11/p1.3 33 26 a in d i/o port 1.3. see port input/output section for complete description. ain1.4/a12/p1.4 32 23 a in d i/o port 1.4. see port input/output section for complete description. ain1.5/a13/p1.5 31 22 a in d i/o port 1.5. see port input/output section for complete description. ain1.6/a14/p1.6 30 21 a in d i/o port 1.6. see port input/output section for complete description. ain1.7/a15/p1.7 29 20 a in d i/o port 1.7. see port input/output section for complete description. a8m/a0/p2.0 46 37 d i/o bit 8 external memory address bus (multiplexed mode) bit 0 external memory address bus (non-multiplexed mode) port 2.0 see port input/output section for complete description. a9m/a1/p2.1 45 36 d i/o port 2.1. see port input/output section for complete description. a10m/a2/p2.2 44 35 d i/o port 2.2. see port input/output section for complete description. a11m/a3/p2.3 43 34 d i/o port 2.3. see port input/output section for complete description. a12m/a4/p2.4 42 33 d i/o port 2.4. see port input/output section for complete description. a13m/a5/p2.5 41 32 d i/o port 2.5. see port input/output section for complete description. table 4.1. pin definitions name pin numbers type description f020 f021 f022 f023
c8051f020/1/2/3 36 rev. 1.4 a14m/a6/p2.6 40 31 d i/o port 2.6. see port input/output section for complete description. a15m/a7/p2.7 39 30 d i/o port 2.7. see port input/output section for complete description. ad0/d0/p3.0 54 47 d i/o bit 0 external memory address/data bus (multiplexed mode) bit 0 external memory data bus (non-multiplexed mode) port 3.0 see port input/output section for complete description. ad1/d1/p3.1 53 46 d i/o port 3.1. see port input/output section for complete description. ad2/d2/p3.2 52 45 d i/o port 3.2. see port input/output section for complete description. ad3/d3/p3.3 51 44 d i/o port 3.3. see port input/output section for complete description. ad4/d4/p3.4 50 43 d i/o port 3.4. see port input/output section for complete description. ad5/d5/p3.5 49 42 d i/o port 3.5. see port input/output section for complete description. ad6/d6/p3.6/ie6 48 39 d i/o port 3.6. see port input/output section for complete description. ad7/d7/p3.7/ie7 47 38 d i/o port 3.7. see port input/output section for complete description. p4.0 98 d i/o port 4.0. see port input/output section for complete description. p4.1 97 d i/o port 4.1. see port input/output section for complete description. p4.2 96 d i/o port 4.2. see port input/output section for complete description. p4.3 95 d i/o port 4.3. see port input/output section for complete description. p4.4 94 d i/o port 4.4. see port input/output section for complete description. ale/p4.5 93 d i/o ale strobe for external memory address bus (multiplexed mode) port 4.5 see port input/output section for complete description. /rd/p4.6 92 d i/o /rd strobe for external memory address bus port 4.6 see port input/output section for complete description. /wr/p4.7 91 d i/o /wr strobe for external memory address bus port 4.7 see port input/output section for complete description. a8/p5.0 88 d i/o bit 8 external memory address bus (non-multiplexed mode) port 5.0 see port input/output section for complete description. a9/p5.1 87 d i/o port 5.1. see port input/output section for complete description. a10/p5.2 86 d i/o port 5.2. see port input/output section for complete description. table 4.1. pin definitions name pin numbers type description f020 f021 f022 f023
c8051f020/1/2/3 rev. 1.4 37 a11/p5.3 85 d i/o port 5.3. see port input/output section for complete description. a12/p5.4 84 d i/o port 5.4. see port input/output section for complete description. a13/p5.5 83 d i/o port 5.5. see port input/output section for complete description. a14/p5.6 82 d i/o port 5.6. see port input/output section for complete description. a15/p5.7 81 d i/o port 5.7. see port input/output section for complete description. a8m/a0/p6.0 80 d i/o bit 8 external memory address bus (multiplexed mode) bit 0 external memory address bus (non-multiplexed mode) port 6.0 see port input/output section for complete description. a9m/a1/p6.1 79 d i/o port 6.1. see port input/output section for complete description. a10m/a2/p6.2 78 d i/o port 6.2. see port input/output section for complete description. a11m/a3/p6.3 77 d i/o port 6.3. see port input/output section for complete description. a12m/a4/p6.4 76 d i/o port 6.4. see port input/output section for complete description. a13m/a5/p6.5 75 d i/o port 6.5. see port input/output section for complete description. a14m/a6/p6.6 74 d i/o port 6.6. see port input/output section for complete description. a15m/a7/p6.7 73 d i/o port 6.7. see port input/output section for complete description. ad0/d0/p7.0 72 d i/o bit 0 external memory address/data bus (multiplexed mode) bit 0 external memory data bus (non-multiplexed mode) port 7.0 see port input/output section for complete description. ad1/d1/p7.1 71 d i/o port 7.1. see port input/output section for complete description. ad2/d2/p7.2 70 d i/o port 7.2. see port input/output section for complete description. ad3/d3/p7.3 69 d i/o port 7.3. see port input/output section for complete description. ad4/d4/p7.4 68 d i/o port 7.4. see port input/output section for complete description. ad5/d5/p7.5 67 d i/o port 7.5. see port input/output section for complete description. ad6/d6/p7.6 66 d i/o port 7.6. see port input/output section for complete description. ad7/d7/p7.7 65 d i/o port 7.7. see port input/output section for complete description. table 4.1. pin definitions name pin numbers type description f020 f021 f022 f023
c8051f020/1/2/3 38 rev. 1.4 c8051f020 c8051f022 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 75 74 73 72 71 70 69 68 67 ad6/d6/p7.6 ad7/d7/p7.7 vdd dgnd p0.0 p0.1 p0.2 p0.3 p0.4 ale/p0.5 /rd/p0.6 /wr/p0.7 ad0/d0/p3.0 ad1/d1/p3.1 ad2/d2/p3.2 ad3/d3/p3.3 a13m/a5/p6.5 a14m/a6/p6.6 a15m/a7/p6.7 ad0/d0/p7.0 ad1/d1/p7.1 ad2/d2/p7.2 ad3/d3/p7.3 ad4/d4/p7.4 ad5/d5/p7.5 dac0 dac1 p4.0 p4.1 p4.2 p4.3 p4.4 ale/p4.5 /rd/p4.6 /wr/p4.7 vdd dgnd a8/p5.0 a9/p5.1 a10/p5.2 a11/p5.3 a12/p5.4 a13/p5.5 a14/p5.6 a15/p5.7 a8m/a0/p6.0 a9m/a1/p6.1 a10m/a2/p6.2 a11m/a3/p6.3 a12m/a4/p6.4 agnd av+ vref agnd av+ vrefd vref0 vref1 ain0.0 ain0.1 ain0.2 ain0.3 ain0.4 ain0.5 ain0.6 ain0.7 tms tck tdi tdo /rst cp1- cp1+ cp0- cp0+ xtal1 xtal2 monen ain1.7/a15/p1.7 ain1.6/a14/p1.6 ain1.5/a13/p1.5 ain1.4/a12/p1.4 vdd dgnd ain1.3/a11/p1.3 ain1.2/a10/p1.2 ain1.1/a9/p1.1 ain1.0/a8/p1.0 a15m/a7/p2.7 a14m/a6/p2.6 a13m/a5/p2.5 a12m/a4/p2.4 a11m/a3/p2.3 a10m/a2/p2.2 a9m/a1/p2.1 a8m/a0/p2.0 ad7/d7/p3.7/ie7 ad6/d6/p3.6/ie6 ad5/d5/p3.5 ad4/d4/p3.4 figure 4.1. tqfp-100 pinout diagram
c8051f020/1/2/3 rev. 1.4 39 a a1 a2 b d d1 e e e1 - 0.05 0.95 0.17 - - - - - - - 1.00 0.22 16.00 14.00 0.50 16.00 14.00 1.20 0.15 1.05 0.27 - - - - - min (mm) nom (mm) max (mm) 100 e a1 b a2 a pin 1 designator 1 e1 e d1 d figure 4.2. tqfp-100 package drawing
c8051f020/1/2/3 40 rev. 1.4 c8051f021 C8051F023 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 dac0 dac1 /rst tdo tdi tck tms vdd dgnd p0.0 p0.1 p0.2 p0.3 p0.4 ale/p0.5 /rd/p0.6 /wr/p0.7 ad0/d0/p3.0 ad1/d1/p3.1 ad2/d2/p3.2 ad3/d3/p3.3 ad4/d4/p3.4 ad5/d5/p3.5 vdd dgnd ad6/d6/p3.6/ie6 ad7/d7/p3.7/ie7 a8m/a0/p2.0 a9m/a1/p2.1 a10m/a2/p2.2 a11m/a3/p2.3 a12m/a4/p2.4 cp1- cp1+ cp0- cp0+ agnd av+ vref vrefa ain0.0 ain0.1 ain0.2 ain0.3 ain0.4 ain0.5 ain0.6 ain0.7 xtal1 xtal2 monen ain1.7/a15/p1.7 ain1.6/a14/p1.6 ain1.5/a13/p1.5 ain1.4/a12/p1.4 vdd dgnd ain1.3/a11/p1.3 ain1.2/a10/p1.2 ain1.1/a9/p1.1 ain1.0/a8/p1.0 a15m/a7/p2.7 a14m/a6/p2.6 a13m/a5/p2.5 figure 4.3. tqfp-64 pinout diagram
c8051f020/1/2/3 rev. 1.4 41 a a1 a2 b d d1 e e e1 - 0.05 0.95 0.17 - - - - - - - - 0.22 12.00 10.00 0.50 12.00 10.00 1.20 0.15 1.05 0.27 - - - - - min (mm) nom (mm) max (mm) 1 64 e e1 e a1 b d d1 pin 1 designator a2 a figure 4.4. tqfp-64 package drawing
c8051f020/1/2/3 42 rev. 1.4 notes
c8051f020/1 rev. 1.4 43 5. adc0 (12-bit adc, c8051f020/1 only) the adc0 subsystem for the c8051f020/1 consists of a 9- channel, configurable anal og multiplexer (amux0), a programmable gain amplifier (pga0), and a 100 ksps, 12-bit successive-approximation- register adc with integrated track-and-hold and programmable window detector (see block diagram in figure 5.1 ). the amux0, pga0, data conversion modes, and window detector are all configurab le under software control via the special function regis - ters shown in figure 5.1 . the voltage reference used by adc0 is selected as described in section ?9. voltage reference (c8051f020/2)? on page 91 for c8051f020/2 devices, or section ?10. voltage reference (c8051f021/3)? on page 93 for c8051f021/3 devices. the adc0 subsystem (adc0, track-and-hold and pga0) is enabled only when the ad0en bit in the adc0 control regi ster (adc0cn) is set to logic 1. the adc0 subsystem is in low power shutdown when this bit is logic 0. 5.1. analog multiplexer and pga eight of the amux channels are availabl e for external measurements while the ninth channel is internally connected to an on-chip temperature sensor (temperature transfer function is shown in figure 5.2 ). amux input pairs can be programmed to operate in either differential or single-ende d mode. this allows the user to select the best measure - ment technique for each input channel, and even accommodates mode cha nges "on-the-fly". th e amux defaults to all single-ended inputs upon reset. there are two registers associated with the amux: th e channel selection register amx0sl ( figure 5.6 ), and the configuratio n register amx0cf ( figure 5.7 ). the table in figure 5.6 shows amux functionality by channel, for each possible configuration. the pga amplifies the amux ou tput signal by an amount determined by the states of the amp0gn2-0 bits in the adc0 configuration register, adc0cf ( figure 5.7 ). the pga can be software-programmed for gains of 0.5, 2, 4, 8 or 16. gain defaults to unity on reset. 12-bit sar adc ref + - av+ temp sensor 12 + - + - + - 9-to-1 amux (se or diff) av+ 24 12 ad0en sysclk + - x ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 start conversion agnd agnd adc0l adc0h adc0ltl adc0lth adc0gtl adc0gth ad0cm timer 3 overflow timer 2 overflow 00 01 10 11 ad0busy (w) cnvstr ad0wint comb. logic amx0cf amx0sl amx0ad0 amx0ad1 amx0ad2 amx0ad3 ain01ic ain23ic ain45ic ain67ic adc0cf amp0gn0 amp0gn1 amp0gn2 ad0sc0 ad0sc1 ad0sc2 ad0sc3 ad0sc4 adc0cn ad0ljst ad0wint ad0cm0 ad0cm1 ad0busy ad0int ad0tm ad0en ad0cm figure 5.1. 12-bit adc0 functional block diagram
c8051f020/1 44 rev. 1.4 the temperature sensor transfer function is shown in figure 5.2 . the output voltage (v temp ) is the pga input when the temperature sensor is selected by bits amx0ad3-0 in register amx0sl; this voltage will be amplified by the pga according to the user-programmed pga settings. 5.2. adc modes of operation adc0 has a maximum conv ersion speed of 100 ksps. the adc0 conversion clock is derived from the system clock divided by the value held in the adcsc bits of register adc0cf. 5.2.1. starting a conversion a conversion can be initiated in one of four ways, depend ing on the programmed states of the adc0 start of conver - sion mode bits (ad0cm1, ad0cm0) in adc0cn. conversions may be initiated by: 1. writing a ?1? to the ad0busy bit of adc0cn; 2. a timer 3 overflow (i.e. timed continuous conversions); 3. a rising edge detected on the external adc convert start signal, cnvstr; 4. a timer 2 overflow (i.e. timed continuous conversions). the ad0busy bit is set to logic 1 during conversion and restored to logic 0 when conversion is complete. the fall - ing edge of ad0busy triggers an interrupt (when enable d) and sets the ad0int interrupt flag (adc0cn.5). con - verted data is available in the adc 0 data word msb and lsb registers, adc0h, adc0l. converted data can be either left or right justified in the ad c0h:adc0l register pair (see example in figure 5.11 ) depending on the pro - grammed state of the ad0ljst bit in the adc0cn register. when initiating conversions by writing a ?1? to ad0busy, the ad0int bit should be polled to determine when a conversion has completed (adc0 interrupts may also be used). the recommended polling procedure is shown below. step 1. write a ?0? to ad0int; step 2. write a ?1? to ad0busy; step 3. poll ad0int for ?1?; step 4. process adc0 data. 0 -50 50 100 (celsius) 0.500 0.600 0.700 0.800 0.900 (volts) v temp = 0.00286(temp c ) + 0.776 for pga gain = 1 1.000 figure 5.2. temperature sensor transfer function
c8051f020/1 rev. 1.4 45 5.2.2. tracking modes the ad0tm bit in register adc0cn controls the adc0 track-and-hold mode. in its default state, the adc0 input is continuously tracked when a conversion is not in progress. when the ad0tm bit is logic 1, adc0 operates in low- power track-and-hold mode. in this mode, each conversion is preceded by a tracking period of 3 sar clocks (after the start-of-conversion signal). when the cnvstr signal is used to ini tiate conversions in low-power tracking mode, adc0 tracks only when cnvstr is low; conversion begins on the rising edge of cnvstr (see figure 5.3 ). track - ing can also be disabled (shutdown) when the entire chip is in low power standby or sleep modes. low-power track- and-hold mode is also useful when amux or pga settings are frequently changed, to ensure that settling time requirements are met (see section ?5.2.3. settling time requirements? on page 46 ). 12345678910111213141516 cnvstr (ad0stm[1:0]=10 ) adc0tm=1 adc0tm=0 timer 2, timer 3 overflow; write '1' to ad0busy (ad0stm[1:0]=00, 01, 11) adc0tm=1 adc0tm=0 a. adc timing for external trigger source b. adc timing for internal trigger sources sar clocks sar clocks 12345678910111213141516 17 18 19 12345678910111213141516 sar clocks track convert low power mode low power or convert track or convert convert track track convert low power mode low power or convert track or convert convert track figure 5.3. 12-bit adc track and conversion example timing
c8051f020/1 46 rev. 1.4 5.2.3. settling time requirements when the adc0 input configuration is changed (i.e., a diff erent mux or pga selection is made), a minimum settling (or tracking) time is required before an accurate conversion can be performe d. this settling time is determined by the adc0 mux resistance, the adc0 sampling capacitance, any external source resi stance, and the accuracy required for the conversion. figure 5.4 shows the equivalent adc0 input circuits for both differential and single-ended modes. notice that the equivalent time constant for both input circuits is the same. the required settling time for a given settling accuracy ( sa ) may be approximated by equation 5.1 . when measuring the temperature sensor output, r total reduces to r mux . note that in low-power tracking mode, three sa r clocks are used for tr acking at the start of every conversion. for most applicat ions, these three sar clocks will meet the tracking requirements. see table 5.1 on page 58 for absolute minimum settling/tracking time requirements. where: sa is the settling accuracy, given as a fraction of an ls b (for example, 0.25 to settle within 1/4 lsb) t is the required settling time in seconds r total is the sum of the adc0 mux resistan ce and any external source resistance. n is the adc resolution in bits (12). equation 5.1. adc0 settling time requirements t 2 n sa ------ - ?? ?? r total c sample ln = r mux = 5k rc input = r mux * c sample r mux = 5k c sample = 10pf c sample = 10pf mux select mux select differential mode ain0.x ain0.y r mux = 5k c sample = 10pf rc input = r mux * c sample mux select single-ended mode ain0.x figure 5.4. adc0 equivalent input circuits
c8051f020/1 rev. 1.4 47 figure 5.5. amx0cf: amux0 conf iguration register (c8051f020/1) bits7-4: unused. read = 0000b; write = don?t care bit3: ain67ic: ain6, ain7 input pair configuration bit 0: ain6 and ain7 are independent single-ended inputs 1: ain6, ain7 are (respectively) +, - differential input pair bit2: ain45ic: ain4, ain5 input pair configuration bit 0: ain4 and ain5 are independent single-ended inputs 1: ain4, ain5 are (respectively) +, - differential input pair bit1: ain23ic: ain2, ain3 input pair configuration bit 0: ain2 and ain3 are independent single-ended inputs 1: ain2, ain3 are (respectively) +, - differential input pair bit0: ain01ic: ain0, ain1 input pair configuration bit 0: ain0 and ain1 are independent single-ended inputs 1: ain0, ain1 are (respectively) +, - differential input pair note: the adc0 data word is in 2?s complement fo rmat for channels confi gured as differential. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - - - ain67ic ain45ic ain23ic ain01ic 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xba
c8051f020/1 48 rev. 1.4 figure 5.6. amx0sl: amux0 channe l select regist er (c8051f020/1) bits7-4: unused. read = 0000b; write = don?t care bits3-0: amx0ad3-0: amx0 address bits 0000-1111b: adc inputs selected per chart below r/w r/w r/w r/w r/w r/w r/w r/w reset value - - - - amx0ad3 amx0ad2 amx0ad1 amx0ad0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xbb amx0ad3-0 0000 0001 0010 0011 0100 0101 0110 0111 1xxx amx0cf bits 3-0 0000 ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 temp sensor 0001 +(ain0) -(ain1) ain2 ain3 ain4 ain5 ain6 ain7 temp sensor 0010 ain0 ain1 +(ain2) -(ain3) ain4 ain5 ain6 ain7 temp sensor 0011 +(ain0) -(ain1) +(ain2) -(ain3) ain4 ain5 ain6 ain7 temp sensor 0100 ain0 ain1 ain2 ain3 +(ain4) -(ain5) ain6 ain7 temp sensor 0101 +(ain0) -(ain1) ain2 ain3 +(ain4) -(ain5) ain6 ain7 temp sensor 0110 ain0 ain1 +(ain2) -(ain3) +(ain4) -(ain5) ain6 ain7 temp sensor 0111 +(ain0) -(ain1) +(ain2) -(ain3) +(ain4) -(ain5) ain6 ain7 temp sensor 1000 ain0 ain1 ain2 ain3 ain4 ain5 +(ain6) -(ain7) temp sensor 1001 +(ain0) -(ain1) ain2 ain3 ain4 ain5 +(ain6) -(ain7) temp sensor 1010 ain0 ain1 +(ain2) -(ain3) ain4 ain5 +(ain6) -(ain7) temp sensor 1011 +(ain0) -(ain1) +(ain2) -(ain3) ain4 ain5 +(ain6) -(ain7) temp sensor 1100 ain0 ain1 ain2 ain3 +(ain4) -(ain5) +(ain6) -(ain7) temp sensor 1101 +(ain0) -(ain1) ain2 ain3 +(ain4) -(ain5) +(ain6) -(ain7) temp sensor 1110 ain0 ain1 +(ain2) -(ain3) +(ain4) -(ain5) +(ain6) -(ain7) temp sensor 1111 +(ain0) -(ain1) +(ain2) -(ain3) +(ain4) -(ain5) +(ain6) -(ain7) temp sensor
c8051f020/1 rev. 1.4 49 figure 5.7. adc0cf: adc0 config uration register (c8051f020/1) bits7-3: ad0sc4-0: adc0 sar conversion clock period bits sar conversion clock is derived from system clock by the following equation, where ad0sc refers to the 5-bit value held in ad0sc4-0, and clk sar0 refers to the desired adc0 sar clock. see table 5.1 on page 58 for sar clock setting requirements. bits2-0: amp0gn2-0: adc0 internal amplifier gain (pga) 000: gain = 1 001: gain = 2 010: gain = 4 011: gain = 8 10x: gain = 16 11x: gain = 0.5 r/w r/w r/w r/w r/w r/w r/w r/w reset value ad0sc4 ad0sc3 ad0sc2 ad0sc1 ad0sc0 amp0gn2 amp0gn1 amp0gn0 11111000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xbc a d 0 sc sysclk clk sar 0 ------------ ---------- -1 ? =
c8051f020/1 50 rev. 1.4 figure 5.8. adc0cn: adc0 co ntrol register (c8051f020/1) bit7: ad0en: adc0 enable bit. 0: adc0 disabled. adc0 is in low-power shutdown. 1: adc0 enabled. adc0 is active and ready for data conversions. bit6: ad0tm: adc track mode bit 0: when the adc is enabled, tracking is continuous unless a conversion is in process 1: tracking defined by adstm1-0 bits bit5: ad0int: adc0 conversion complete interrupt flag. this flag must be cleared by software. 0: adc0 has not completed a data conversion since the last time this flag was cleared. 1: adc0 has completed a data conversion. bit4: ad0busy: adc0 busy bit. read: 0: adc0 conversion is complete or a conversion is not currently in progress. ad0int is set to logic 1 on the falling edge of ad0busy. 1: adc0 conversion is in progress. write: 0: no effect. 1: initiates adc0 conversion if ad0stm1-0 = 00b bit3-2: ad0cm1-0: adc0 start of conversion mode select. if ad0tm = 0: 00: adc0 conversion initiated on every write of ?1? to ad0busy. 01: adc0 conversion initiated on overflow of timer 3. 10: adc0 conversion initiated on rising edge of external cnvstr. 11: adc0 conversion initiated on overflow of timer 2. if ad0tm = 1: 00: tracking starts with the write of ?1? to ad0busy and lasts for 3 sar clocks, followed by con- version. 01: tracking started by the overflow of timer 3 and last for 3 sar clocks, followed by conversion. 10: adc0 tracks only when cnvstr input is logic low; conversion starts on rising cnvstr edge. 11: tracking started by the overflow of timer 2 and last for 3 sar clocks, followed by conversion. bit1: ad0wint: adc0 window compare interrupt flag. this bit must be cleared by software. 0: adc0 window comparison data match has not occurred since this flag was last cleared. 1: adc0 window comparison data match has occurred. bit0: ad0ljst: adc0 left justify select. 0: data in adc0h:adc0l registers are right-justified. 1: data in adc0h:adc0l re gisters are left-justified. r/w r/w r/w r/w r/w r/w r/w r/w reset value ad0en ad0tm ad0int ad0busy ad0cm1 ad0cm0 ad0wint ad0ljst 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xe8
c8051f020/1 rev. 1.4 51 figure 5.9. adc0h: adc0 data word msb register (c8051f020/1) bits7-0: adc0 data word high-order bits. for ad0ljst = 0: bits 7-4 are the sign extension of bit3. bits 3-0 are the upper 4 bits of the 12-bit adc0 data word. for ad0ljst = 1: bits 7-0 are the most-significant bits of the 12-bit adc0 data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xbf figure 5.10. adc0l: adc0 data word lsb register (c8051f020/1) bits7-0: adc0 data word low-order bits. for ad0ljst = 0: bits 7-0 are the lower 8 bits of the 12-bit adc0 data word. for ad0ljst = 1: bits 7-4 are the lower 4 bits of the 12-bit adc0 data word. bits3-0 will always read ?0?. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xbe
c8051f020/1 52 rev. 1.4 figure 5.11. adc0 data word example (c8051f020/1) 12-bit adc0 data word appears in th e adc0 data word registers as follows: adc0h[3:0]:adc0l[7:0], if ad0ljst = 0 (adc0h[7:4] will be sign-extension of adc0h.3 for a differential reading, otherwise = 0000b). adc0h[7:0]:adc0l[7:4], if ad0ljst = 1 (adc0l[3:0] = 0000b). example: adc0 data word conversion map, ain0 input in single-ended mode (amx0cf = 0x00, amx0sl = 0x00) example: adc0 data word conversion map, ain0-ain1 differential input pair (amx0cf = 0x01, amx0sl = 0x00) for ad0ljst = 0: ; ?n? = 12 for single-ended ; ?n?=11 for differential. ain0-agnd (volts) adc0h:adc0l (ad0ljst = 0) adc0h:adc0l (ad0ljst = 1) vref * (4095/4096) 0x0fff 0xfff0 vref / 2 0x0800 0x8000 vref * (2047/4096) 0x07ff 0x7ff0 0 0x0000 0x0000 ain0-agnd (volts) adc0h:adc0l (ad0ljst = 0) adc0h:adc0l (ad0ljst = 1) vref * (2047/2048) 0x07ff 0x7ff0 vref / 2 0x0400 0x4000 vref * (1/2048) 0x0001 0x0010 0 0x0000 0x0000 -vref * (1/2048) 0xffff (-1d) 0xfff0 -vref / 2 0xfc00 (-1024d) 0xc000 -vref 0xf800 (-2048d) 0x8000 code vin gain vref --------------- 2 n =
c8051f020/1 rev. 1.4 53 5.3. adc0 programmable window detector the adc0 programmable window detector continuously compares the adc0 output to user-programmed limits, and notifies the system when an out-of-bound condition is det ected. this is especially effective in an interrupt-driven system, saving code space and cpu bandwidth while deliver ing faster system response times. the window detector interrupt flag (ad0wint in adc0cn) can also be used in polled mode. th e high and low bytes of the reference words are loaded into the adc0 greater-than and adc 0 less-than registers (adc0gth, adc0gtl, adc0lth, and adc0ltl). reference compar isons are shown starting on page 54 . notice that the window detector flag can be asserted when the measured data is inside or outside the user-programmed limits, depending on the programming of the adc0gtx and adc0ltx registers. figure 5.12. adc0gth: adc0 greater-than data high byte register (c8051f020/1) bits7-0: high byte of adc0 greater-than data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc5 figure 5.13. adc0gtl: adc0 greater-th an data low byte register (c8051f020/1) bits7-0: low byte of adc0 greater-than data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc4 bits7-0: high byte of adc0 less-than data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc7 figure 5.14. adc0lth: adc0 less-than data high byte register (c8051f020/1) figure 5.15. adc0ltl: adc0 less-than data low byte register (c8051f020/1) bits7-0: low byte of adc0 less-than data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc6
c8051f020/1 54 rev. 1.4 figure 5.16. 12-bit adc0 window interrupt e xample: right justif ied single-ended data given: amx0sl = 0x00, amx0cf = 0x00 ad0ljst = ?0?, adc0lth:adc0ltl = 0x0200, adc0gth:adc0gtl = 0x0100. an adc0 end of conversi on will cause an adc0 window compare interrupt (ad0wint = ?1?) if the resulting adc0 data word is < 0x0200 and > 0x0100. given: amx0sl = 0x00, amx0cf = 0x00, ad0ljst = ?0?, adc0lth:adc0ltl = 0x0100, adc0gth:adc0gtl = 0x0200. an adc0 end of conversion will cause an adc0 window compare interrupt (ad0wint = ?1?) if the resulting adc0 data word is > 0x0200 or < 0x0100. 0x0fff 0x0201 0x0200 0x01ff 0x0101 0x0100 0x00ff 0x0000 ad0wint=1 ad0wint not affected ad0wint not affected adc data word 0x0fff 0x0201 0x0200 0x01ff 0x0101 0x0100 0x00ff 0x0000 ad0wint=1 ad0wint not affected ad0wint=1 adc0lth:adc0ltl adc0gth:adc0gtl adc data word adc0gth:adc0gtl adc0lth:adc0ltl 0 input voltage (ad0 - agnd) ref x (4095/4096) ref x (256/4096) ref x (512/4096) 0 input voltage (ad0 - agnd) ref x (4095/4096) ref x (256/4096) ref x (512/4096)
c8051f020/1 rev. 1.4 55 0x07ff 0x0101 0x0100 0x00ff 0x0000 0xffff 0xfffe 0xf800 ad0wint=1 ad0wint not affected ad0wint not affected 0x07ff 0x0101 0x0100 0x00ff 0x0000 0xffff 0xfffe 0xf800 ad0wint=1 ad0wint not affected -ref input voltage (ad0 - ad1) ad0wint=1 ref x (2047/2048) adc0lth:adc0ltl adc0gth:adc0gtl adc data word adc data word adc0lth:adc0ltl adc0gth:adc0gtl ref x (256/2048) ref x (-1/2048) -ref input voltage (ad0 - ad1) ref x (2047/2048) ref x (256/2048) ref x (-1/2048) figure 5.17. 12-bit adc0 window interrupt ex ample: right justified differential data given: amx0sl = 0x00, amx0cf = 0x01, ad0ljst = ?0?, adc0lth:adc0ltl = 0x0100, adc0gth:adc0gtl = 0xffff. an adc0 end of conversi on will cause an adc0 window compare interrupt (ad0wint = ?1?) if the resulting adc0 data word is < 0x0100 and > 0xffff. (in two?s-complement math, 0xffff = -1.) given: amx0sl = 0x00, amx0cf = 0x01, ad0ljst = ?0?, adc0lth:adc0ltl = 0xffff, adc0gth:adc0gtl = 0x0100. an adc0 end of conversion will cause an adc0 window compare interrupt (ad0wint = ?1?) if the resulting adc0 data word is < 0xffff or > 0x0100. (in two?s-complement math, 0xffff = -1.)
c8051f020/1 56 rev. 1.4 0xfff0 0x2010 0x2000 0x1ff0 0x1010 0x1000 0x0ff0 0x0000 ad0wint=1 ad0wint not affected ad0wint not affected adc data word 0xfff0 0x2010 0x2000 0x1ff0 0x1010 0x1000 0x0ff0 0x0000 ad0wint=1 ad0wint not affected ad0wint=1 adc0lth:adc0ltl adc0gth:adc0gtl adc data word adc0gth:adc0gtl adc0lth:adc0ltl 0 input voltage (ad0 - agnd) ref x (4095/4096) ref x (256/4096) ref x (512/4096) 0 input voltage (ad0 - agnd) ref x (4095/4096) ref x (256/4096) ref x (512/4096) figure 5.18. 12-bit adc0 window interrupt e xample: left justified single-ended data given: amx0sl = 0x00, amx0cf = 0x00, ad0ljst = ?1?, adc0lth:adc0ltl = 0x2000, adc0gth:adc0gtl = 0x1000. an adc0 end of conversi on will cause an adc0 window compare interrupt (ad0wint = ?1?) if the resulting adc0 data word is < 0x2000 and > 0x1000. given: amx0sl = 0x00, amx0cf = 0x00, ad0ljst = ?1? adc0lth:adc0ltl = 0x1000, adc0gth:adc0gtl = 0x2000. an adc0 end of conversion will cause an adc0 window compare interrupt (ad0wint = ?1?) if the resulting adc0 data word is < 0x1000 or > 0x2000.
c8051f020/1 rev. 1.4 57 0x7ff0 0x1010 0x1000 0x0ff0 0x0000 0xfff0 0xffe0 0x8000 ad0wint=1 ad0wint not affected ad0wint not affected 0x7ff0 0x1010 0x1000 0x0ff0 0x0000 0xfff0 0xffe0 0x8000 ad0wint=1 ad0wint not affected -ref input voltage (ad0 - ad1) ad0wint=1 ref x (2047/2048) adc0lth:adc0ltl adc0gth:adc0gtl adc data word adc data word adc0lth:adc0ltl adc0gth:adc0gtl ref x (256/2048) ref x (-1/2048) -ref input voltage (ad0 - ad1) ref x (2047/2048) ref x (256/2048) ref x (-1/2048) figure 5.19. 12-bit adc0 window interrupt exam ple: left justifie d differential data given: amx0sl = 0x00, amx0cf = 0x01, ad0ljst = ?1?, adc0lth:adc0ltl = 0x1000, adc0gth:adc0gtl = 0xfff0. an adc0 end of conversi on will cause an adc0 window compare interrupt (ad0wint = ?1?) if the resulting adc0 data word is < 0x1000 and > 0xfff0. (two?s-complement math.) given: amx0sl = 0x00, amx0cf = 0x01, ad0ljst = ?1?, adc0lth:adc0ltl = 0xfff0, adc0gth:adc0gtl = 0x1000. an adc0 end of conversion will cause an adc0 window compare interrupt (ad0wint = ?1?) if the resulting adc0 data word is < 0xfff0 or > 0x1000. (two?s-complement math.)
c8051f020/1 58 rev. 1.4 table 5.1. 12-bit adc0 electrical characteristics (c8051f020/1) vdd = 3.0v, av+ = 3.0v, vref = 2.40v (refbe=0), pga gain = 1, -40c to +85c unless otherwise specified parameter conditions min typ max units dc accuracy resolution 12 bits integral nonlinearity 1 lsb differential nonlinearity guaranteed monotonic 1 lsb offset error -31 lsb full scale error differential mode -73 lsb offset temperature coefficient 0.25 ppm/c dynamic performance (10 khz sine-wave input, 0 to 1 db below full scale, 100 ksps signal-to-noise plus distortion 66 db total harmonic distortion up to the 5 th harmonic -75 db spurious-free dynamic range 80 db conversion rate sar clock frequency 2.5 mhz conversion time in sar clocks 16 clocks track/hold acquisition time 1.5 s throughput rate 100 ksps analog inputs input voltage range single-ended operation 0 vref v *common-mode voltage range differential operation agnd av + v input capacitance 10 pf temperature sensor nonlinearity -1.0 +1.0 c absolute accuracy 3 c gain pga gain = 1 2.86 mv/c offset pga gain = 1, temp = 0c 0.776 v power specifications power supply current (av+ sup - plied to adc) operating mode, 100 ksps 450 900 a power supply rejection 0.3 mv/v
c8051f022/3 rev. 1.4 59 6. adc0 (10-bit adc, c8051f022/3 only) the adc0 subsystem for the c8051f022/3 consists of a 9- channel, configurable anal og multiplexer (amux0), a programmable gain amplifier (pga0), and a 100 ksps, 10-bit successive-approximation- register adc with integrated track-and-hold and programmable window detector (see block diagram in figure 6.1 ). the amux0, pga0, data conversion modes, and window detector are all configurab le under software control via the special function regis - ters shown in figure 6.1 . the voltage reference used by adc0 is selected as described in section ?9. voltage reference (c8051f020/2)? on page 91 for c8051f020/2 devices, or section ?10. voltage reference (c8051f021/3)? on page 93 for c8051f021/3 devices. the adc0 subsystem (adc0, track-and-hold and pga0) is enabled only when the ad0en bit in the adc0 control regi ster (adc0cn) is set to logic 1. the adc0 subsystem is in low power shutdown when this bit is logic 0. 6.1. analog multiplexer and pga eight of the amux channels are availabl e for external measurements while the ninth channel is internally connected to an on-chip temperature sensor (temperature transfer function is shown in figure 6.2 ). amux input pairs can be programmed to operate in either differential or single-ende d mode. this allows the user to select the best measure - ment technique for each input channel, and even accommodates mode cha nges "on-the-fly". th e amux defaults to all single-ended inputs upon reset. there are two registers associated with the amux: th e channel selection register amx0sl ( figure 6.6 ), and the configuratio n register amx0cf ( figure 6.7 ). the table in figure 6.6 shows amux functionality by channel, for each possible configuration. the pga amplifies the amux ou tput signal by an amount determined by the states of the amp0gn2-0 bits in the adc0 configuration register, adc0cf ( figure 6.7 ). the pga can be software-programmed for gains of 0.5, 2, 4, 8 or 16. gain defaults to unity on reset. 10-bit sar adc ref + - av+ temp sensor 10 + - + - + - 9-to-1 amux (se or diff) av+ 20 10 ad0en sysclk + - x ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 start conversion agnd agnd adc0l adc0h adc0ltl adc0lth adc0gtl adc0gth ad0cm timer 3 overflow timer 2 overflow 00 01 10 11 ad0busy (w) cnvstr ad0wint comb. logic amx0sl amx0ad0 amx0ad1 amx0ad2 amx0ad3 amx0cf ain01ic ain23ic ain45ic ain67ic adc0cf amp0gn0 amp0gn1 amp0gn2 ad0sc0 ad0sc1 ad0sc2 ad0sc3 ad0sc4 adc0cn ad0ljst ad0wint ad0cm0 ad0cm1 ad0busy ad0int ad0tm ad0en ad0cm figure 6.1. 10-bit adc0 functional block diagram
c8051f022/3 60 rev. 1.4 the temperature sensor transfer function is shown in figure 6.2 . the output voltage (v temp ) is the pga input when the temperature sensor is selected by bits amx0ad3-0 in register amx0sl; this voltage will be amplified by the pga according to the user-programmed pga settings. 6.2. adc modes of operation adc0 has a maximum conv ersion speed of 100 ksps. the adc0 conversion clock is derived from the system clock divided by the value held in the adcsc bits of register adc0cf. 6.2.1. starting a conversion a conversion can be initiated in one of four ways, depend ing on the programmed states of the adc0 start of conver - sion mode bits (ad0cm1, ad0cm0) in adc0cn. conversions may be initiated by: 1. writing a ?1? to the ad0busy bit of adc0cn; 2. a timer 3 overflow (i.e. timed continuous conversions); 3. a rising edge detected on the external adc convert start signal, cnvstr; 4. a timer 2 overflow (i.e. timed continuous conversions). the ad0busy bit is set to logic 1 during conversion and restored to logic 0 when conversion is complete. the fall - ing edge of ad0busy triggers an interrupt (when enable d) and sets the ad0int interrupt flag (adc0cn.5). con - verted data is available in the adc 0 data word msb and lsb registers, adc0h, adc0l. converted data can be either left or right justified in the ad c0h:adc0l register pair (see example in figure 6.11 ) depending on the pro - grammed state of the ad0ljst bit in the adc0cn register. when initiating conversions by writing a ?1? to ad0busy, the ad0int bit should be polled to determine when a conversion has completed (adc0 interrupts may also be used). the recommended polling procedure is shown below. step 1. write a ?0? to ad0int; step 2. write a ?1? to ad0busy; step 3. poll ad0int for ?1?; step 4. process adc0 data. 0 -50 50 100 (celsius) 0.500 0.600 0.700 0.800 0.900 (volts) v temp = 0.00286(temp c ) + 0.776 for pga gain = 1 1.000 figure 6.2. temperature sensor transfer function
c8051f022/3 rev. 1.4 61 6.2.2. tracking modes the ad0tm bit in register adc0cn controls the adc0 track-and-hold mode. in its default state, the adc0 input is continuously tracked when a conversion is not in progress. when the ad0tm bit is logic 1, adc0 operates in low- power track-and-hold mode. in this mode, each conversion is preceded by a tracking period of 3 sar clocks (after the start-of-conversion signal). when the cnvstr signal is used to ini tiate conversions in low-power tracking mode, adc0 tracks only when cnvstr is low; conversion begins on the rising edge of cnvstr (see figure 6.3 ). track - ing can also be disabled (shutdown) when the entire chip is in low power standby or sleep modes. low-power track- and-hold mode is also useful when amux or pga settings are frequently changed, to ensure that settling time requirements are met (see section ?6.2.3. settling time requirements? on page 62 ). 12345678910111213141516 cnvstr (ad0stm[1:0]=10 ) adc0tm=1 adc0tm=0 timer 2, timer 3 overflow; write '1' to ad0busy (ad0stm[1:0]=00, 01, 11) adc0tm=1 adc0tm=0 a. adc timing for external trigger source b. adc timing for internal trigger sources sar clocks sar clocks 12345678910111213141516 17 18 19 12345678910111213141516 sar clocks track convert low power mode low power or convert track or convert convert track track convert low power mode low power or convert track or convert convert track figure 6.3. 10-bit adc track and conversion example timing
c8051f022/3 62 rev. 1.4 6.2.3. settling time requirements when the adc0 input configuration is changed (i.e., a diff erent mux or pga selection is made), a minimum settling (or tracking) time is required before an accurate conversion can be performe d. this settling time is determined by the adc0 mux resistance, the adc0 sampling capacitance, any external source resi stance, and the accuracy required for the conversion. figure 6.4 shows the equivalent adc0 input circuits for both differential and single-ended modes. notice that the equivalent time constant for both input circuits is the same. the required settling time for a given settling accuracy ( sa ) may be approximated by equation 6.1 . when measuring the temperature sensor output, r total reduces to r mux . note that in low-power tracking mode, three sa r clocks are used for tr acking at the start of every conversion. for most applicatio ns, these three sar clocks will meet the settling time requirements. see table 6.1 on page 74 for minimum settling/tracking time requirements. where: sa is the settling accuracy, given as a fraction of an ls b (for example, 0.25 to settle within 1/4 lsb) t is the required settling time in seconds r total is the sum of the adc0 mux resistan ce and any external source resistance. n is the adc resolution in bits (10). equation 6.1. adc0 settling time requirements t 2 n sa ------ - ?? ?? r total c sample ln = r mux = 5k rc input = r mux * c sample r mux = 5k c sample = 10pf c sample = 10pf mux select mux select differential mode ain0.x ain0.y r mux = 5k c sample = 10pf rc input = r mux * c sample mux select single-ended mode ain0.x figure 6.4. adc0 equivalent input circuits
c8051f022/3 rev. 1.4 63 figure 6.5. amx0cf: amux0 conf iguration register (c8051f022/3) bits7-4: unused. read = 0000b; write = don?t care bit3: ain67ic: ain6, ain7 input pair configuration bit 0: ain6 and ain7 are independent single-ended inputs 1: ain6, ain7 are (respectively) +, - differential input pair bit2: ain45ic: ain4, ain5 input pair configuration bit 0: ain4 and ain5 are independent single-ended inputs 1: ain4, ain5 are (respectively) +, - differential input pair bit1: ain23ic: ain2, ain3 input pair configuration bit 0: ain2 and ain3 are independent single-ended inputs 1: ain2, ain3 are (respectively) +, - differential input pair bit0: ain01ic: ain0, ain1 input pair configuration bit 0: ain0 and ain1 are independent single-ended inputs 1: ain0, ain1 are (respectively) +, - differential input pair note: the adc0 data word is in 2?s complement fo rmat for channels confi gured as differential. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - - - ain67ic ain45ic ain23ic ain01ic 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xba
c8051f022/3 64 rev. 1.4 figure 6.6. amx0sl: amux0 channe l select regist er (c8051f022/3) bits7-4: unused. read = 0000b; write = don?t care bits3-0: amx0ad3-0: amx0 address bits 0000-1111b: adc inputs selected per chart below r/w r/w r/w r/w r/w r/w r/w r/w reset value - - - - amx0ad3 amx0ad2 amx0ad1 amx0ad0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xbb amx0ad3-0 0000 0001 0010 0011 0100 0101 0110 0111 1xxx amx0cf bits 3-0 0000 ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 temp sensor 0001 +(ain0) -(ain1) ain2 ain3 ain4 ain5 ain6 ain7 temp sensor 0010 ain0 ain1 +(ain2) -(ain3) ain4 ain5 ain6 ain7 temp sensor 0011 +(ain0) -(ain1) +(ain2) -(ain3) ain4 ain5 ain6 ain7 temp sensor 0100 ain0 ain1 ain2 ain3 +(ain4) -(ain5) ain6 ain7 temp sensor 0101 +(ain0) -(ain1) ain2 ain3 +(ain4) -(ain5) ain6 ain7 temp sensor 0110 ain0 ain1 +(ain2) -(ain3) +(ain4) -(ain5) ain6 ain7 temp sensor 0111 +(ain0) -(ain1) +(ain2) -(ain3) +(ain4) -(ain5) ain6 ain7 temp sensor 1000 ain0 ain1 ain2 ain3 ain4 ain5 +(ain6) -(ain7) temp sensor 1001 +(ain0) -(ain1) ain2 ain3 ain4 ain5 +(ain6) -(ain7) temp sensor 1010 ain0 ain1 +(ain2) -(ain3) ain4 ain5 +(ain6) -(ain7) temp sensor 1011 +(ain0) -(ain1) +(ain2) -(ain3) ain4 ain5 +(ain6) -(ain7) temp sensor 1100 ain0 ain1 ain2 ain3 +(ain4) -(ain5) +(ain6) -(ain7) temp sensor 1101 +(ain0) -(ain1) ain2 ain3 +(ain4) -(ain5) +(ain6) -(ain7) temp sensor 1110 ain0 ain1 +(ain2) -(ain3) +(ain4) -(ain5) +(ain6) -(ain7) temp sensor 1111 +(ain0) -(ain1) +(ain2) -(ain3) +(ain4) -(ain5) +(ain6) -(ain7) temp sensor
c8051f022/3 rev. 1.4 65 figure 6.7. adc0cf: adc0 config uration register (c8051f022/3) bits7-3: ad0sc4-0: adc0 sar conversion clock period bits sar conversion clock is derived from system clock by the following equation, where ad0sc refers to the 5-bit value held in ad0sc4-0, and clk sar0 refers to the desired adc0 sar clock. see table 6.1 on page 74 for sar clock setting requirements. bits2-0: amp0gn2-0: adc0 internal amplifier gain (pga) 000: gain = 1 001: gain = 2 010: gain = 4 011: gain = 8 10x: gain = 16 11x: gain = 0.5 r/w r/w r/w r/w r/w r/w r/w r/w reset value ad0sc4 ad0sc3 ad0sc2 ad0sc1 ad0sc0 amp0gn2 amp0gn1 amp0gn0 11111000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xbc a d 0 sc sysclk clk sar 0 ------------ ---------- -1 ? =
c8051f022/3 66 rev. 1.4 figure 6.8. adc0cn: adc0 co ntrol register (c8051f022/3) bit7: ad0en: adc0 enable bit. 0: adc0 disabled. adc0 is in low-power shutdown. 1: adc0 enabled. adc0 is active and ready for data conversions. bit6: ad0tm: adc track mode bit 0: when the adc is enabled, tracking is continuous unless a conversion is in process 1: tracking defined by adstm1-0 bits bit5: ad0int: adc0 conversion complete interrupt flag. this flag must be cleared by software. 0: adc0 has not completed a data conversion since the last time this flag was cleared. 1: adc0 has completed a data conversion. bit4: ad0busy: adc0 busy bit. read: 0: adc0 conversion is complete or a conversion is not currently in progress. ad0int is set to logic 1 on the falling edge of ad0busy. 1: adc0 conversion is in progress. write: 0: no effect. 1: initiates adc0 conversion if ad0stm1-0 = 00b bit3-2: ad0cm1-0: adc0 start of conversion mode select. if ad0tm = 0: 00: adc0 conversion initiated on every write of ?1? to ad0busy. 01: adc0 conversion initiated on overflow of timer 3. 10: adc0 conversion initiated on rising edge of external cnvstr. 11: adc0 conversion initiated on overflow of timer 2. if ad0tm = 1: 00: tracking starts with the write of ?1? to ad0busy and lasts for 3 sar clocks, followed by con- version. 01: tracking started by the overflow of timer 3 and last for 3 sar clocks, followed by conversion. 10: adc0 tracks only when cnvstr input is logic low; conversion starts on rising cnvstr edge. 11: tracking started by the overflow of timer 2 and last for 3 sar clocks, followed by conversion. bit1: ad0wint: adc0 window compare interrupt flag. this bit must be cleared by software. 0: adc0 window comparison data match has not occurred since this flag was last cleared. 1: adc0 window comparison data match has occurred. bit0: ad0ljst: adc0 left justify select. 0: data in adc0h:adc0l registers are right-justified. 1: data in adc0h:adc0l re gisters are left-justified. r/w r/w r/w r/w r/w r/w r/w r/w reset value ad0en ad0tm ad0int ad0busy ad0cm1 ad0cm0 ad0wint ad0ljst 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xe8
c8051f022/3 rev. 1.4 67 figure 6.9. adc0h: adc0 data word msb register (c8051f022/3) bits7-0: adc data word high-order bits. for adljst = 0: bits 7-2 are the sign extension of bit1. bits 1-0 are the upper 2 bits of the 10-bit adc data word. for adljst = 1: bits 7-0 are the most-significant bits of the 10-bit adc data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xbf figure 6.10. adc0l: adc0 data word lsb register (c8051f022/3) bits7-0: adc data word low-order bits. for adljst = 0: bits 7-0 are the lower 8 bits of the 10-bit adc data word. for adljst = 1: bits 7-6 are the lower 2 bits of the 10-bit adc data word. bits 5-0 will always read ?0?. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xbe
c8051f022/3 68 rev. 1.4 figure 6.11. adc0 data word example (c8051f022/3) 10-bit adc data word ap pears in the adc data word registers as follows: adc0h[1:0]:adc0l[7:0], if adljst = 0 (adc0h[7:2] will be sign-extension of adc0h.1 for a differential reading, otherwise = 000000b). adc0h[7:0]:adc0l[7:6], if adljst = 1 (adc0l[5:0] = 000000b). example: adc data word conversion map, ain0 input in single-ended mode (amx0cf = 0x00, amx0sl = 0x00) example: adc data word conversion map, ain0-ain1 differential input pair (amx0cf = 0x01, amx0sl = 0x00) adljst = 0: ; ?n? = 10 for single-ended ; ?n?=9 for differential. ain0-agnd (volts) adc0h:adc0l (adljst = 0) adc0h:adc0l (adljst = 1) vref * (1023/1024) 0x03ff 0xffc0 vref / 2 0x0200 0x8000 vref * (511/1024) 0x01ff 0x7fc0 0 0x0000 0x0000 ain0-agnd (volts) adc0h:adc0l (adljst = 0) adc0h:adc0l (adljst = 1) vref * (511/512) 0x01ff 0x7fc0 vref / 2 0x0100 0x4000 vref * (1/512) 0x0001 0x0040 0 0x0000 0x0000 -vref * (1/512) 0xffff (-1) 0xffc0 -vref / 2 0xff00 (-256) 0xc000 -vref 0xfe00 (-512) 0x8000 code vin gain vref --------------- 2 n =
c8051f022/3 rev. 1.4 69 6.3. adc0 programmable window detector the adc0 programmable window detector continuously compares the adc0 output to user-programmed limits, and notifies the system when an out-of-bound condition is det ected. this is especially effective in an interrupt-driven system, saving code space and cpu bandwidth while deliver ing faster system response times. the window detector interrupt flag (ad0wint in adc0cn) can also be used in polled mode. th e high and low bytes of the reference words are loaded into the adc0 greater-than and adc 0 less-than registers (adc0gth, adc0gtl, adc0lth, and adc0ltl). reference compar isons are shown starting on page 70 . notice that the window detector flag can be asserted when the measured data is inside or outside the user-programmed limits, depending on the programming of the adc0gtx and adc0ltx registers. figure 6.12. adc0gth: adc0 greater-than data high byte register (c8051f022/3) bits7-0: high byte of adc0 greater-than data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc5 figure 6.13. adc0gtl: adc0 greater-th an data low byte register (c8051f022/3) bits7-0: low byte of adc0 greater-than data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc4 bits7-0: high byte of adc0 less-than data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc7 figure 6.14. adc0lth: adc0 less-than data high byte register (c8051f022/3) figure 6.15. adc0ltl: adc0 less-than data low byte register (c8051f022/3) bits7-0: low byte of adc0 less-than data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc6
c8051f022/3 70 rev. 1.4 figure 6.16. 10-bit adc0 window interrupt e xample: right justif ied single-ended data given: amx0sl = 0x00, amx0cf = 0x00, adljst = 0, adc0lth:adc0ltl = 0x0200, adc0gth:adc0gtl = 0x0100. an adc end of conversi on will cause an adc window compare interrupt (adwint=1) if the resulting adc data word is < 0x0200 and > 0x0100. given: amx0sl = 0x00, amx0cf = 0x00, adljst = 0, adc0lth:adc0ltl = 0x0100, adc0gth:adc0gtl = 0x0200. an adc end of conversi on will cause an adc window compare interrupt (adwint=1) if the resulting adc data word is > 0x0200 or < 0x0100. 0x03ff 0x0201 0x0200 0x01ff 0x0101 0x0100 0x00ff 0x0000 adwint=1 adwint not affected adwint not affected adc data word 0x03ff 0x0201 0x0200 0x01ff 0x0101 0x0100 0x00ff 0x0000 adwint=1 adwint not affected adwint=1 adc0lth:adc0ltl adc0gth:adc0gtl adc data word adc0gth:adc0gtl adc0lth:adc0ltl 0 input voltage (ad0 - agnd) ref x (1023/1024) ref x (256/1024) ref x (512/1024) 0 input voltage (ad0 - agnd) ref x (1023/1024) ref x (256/1024) ref x (512/1024)
c8051f022/3 rev. 1.4 71 0x01ff 0x0101 0x0100 0x00ff 0x0000 0xffff 0xfffe 0xfe00 adwint=1 adwint not affected adwint not affected 0x01ff 0x0101 0x0100 0x00ff 0x0000 0xffff 0xfffe 0xfe00 adwint=1 adwint not affected -ref input voltage (ad0 - ad1) adwint=1 ref x (511/512) adc0lth:adc0ltl adc0gth:adc0gtl adc data word adc data word adc0lth:adc0ltl adc0gth:adc0gtl ref x (256/512) ref x (-1/512) -ref input voltage (ad0 - ad1) ref x (511/512) ref x (256/512) ref x (-1/512) figure 6.17. 10-bit adc0 window interrupt ex ample: right justified differential data given: amx0sl = 0x00, amx0cf = 0x01, adljst = 0, adc0lth:adc0ltl = 0x0100, adc0gth:adc0gtl = 0xffff. an adc end of conversi on will cause an adc window compare interrupt (adwint=1) if the resulting adc data word is < 0x0100 and > 0xffff. (in two?s-complement math, 0xffff = -1.) given: amx0sl = 0x00, amx0cf = 0x01, adljst = 0, adc0lth:adc0ltl = 0xffff, adc0gth:adc0gtl = 0x0100. an adc end of conversi on will cause an adc window compare interrupt (adwint=1) if the resulting adc data word is < 0xffff or > 0x0100. (in two?s-complement math, 0xffff = -1.)
c8051f022/3 72 rev. 1.4 0xffc0 0x8040 0x8000 0x7fc0 0x4040 0x4000 0x3fc0 0x0000 adwint=1 adwint not affected adwint not affected adc data word 0xffc0 0x8040 0x8000 0x7fc0 0x4040 0x4000 0x3fc0 0x0000 adwint=1 adwint not affected adwint=1 adc0lth:adc0ltl adc0gth:adc0gtl adc data word adc0gth:adc0gtl adc0lth:adc0ltl 0 input voltage (ad0 - agnd) ref x (1023/1024) ref x (256/1024) ref x (512/1024) 0 input voltage (ad0 - agnd) ref x (1023/1024) ref x (256/1024) ref x (512/1024) figure 6.18. 10-bit adc0 window interrupt e xample: left justified single-ended data given: amx0sl = 0x00, amx0cf = 0x00, adljst = 1, adc0lth:adc0ltl = 0x8000, adc0gth:adc0gtl = 0x4000. an adc end of conversi on will cause an adc window compare interrupt (adwint=1) if the resulting adc data word is < 0x8000 and > 0x4000. given: amx0sl = 0x00, amx0cf = 0x00, adljst = 1, adc0lth:adc0ltl = 0x4000, adc0gth:adc0gtl = 0x8000. an adc end of conversi on will cause an adc window compare interrupt (adwint=1) if the resulting adc data word is < 0x4000 or > 0x8000.
c8051f022/3 rev. 1.4 73 0x7fc0 0x2040 0x2000 0x1fc0 0x0000 0xffc0 0xff80 0x8000 adwint=1 adwint not affected adwint not affected 0x7fc0 0x2040 0x2000 0x1fc0 0x0000 0xffc0 0xff80 0x8000 adwint=1 adwint not affected -ref input voltage (ad0 - ad1) adwint=1 ref x (511/512) adc0lth:adc0ltl adc0gth:adc0gtl adc data word adc data word adc0lth:adc0ltl adc0gth:adc0gtl ref x (128/512) ref x (-1/512) -ref input voltage (ad0 - ad1) ref x (511/512) ref x (128/512) ref x (-1/512) figure 6.19. 10-bit adc0 window interrupt exam ple: left justifie d differential data given: amx0sl = 0x00, amx0cf = 0x01, adljst = 1, adc0lth:adc0ltl = 0x2000, adc0gth:adc0gtl = 0xffc0. an adc end of conversi on will cause an adc window compare interrupt (adwint=1) if the resulting adc data word is < 0x2000 and > 0xffc0. (two?s-complement math.) given: amx0sl = 0x00, amx0cf = 0x01, adljst = 1, adc0lth:adc0ltl = 0xffc0, adc0gth:adc0gtl = 0x2000. an adc end of conversi on will cause an adc window compare interrupt (adwint=1) if the resulting adc data word is < 0xffc0 or > 0x2000. (two?s-complement math.)
c8051f022/3 74 rev. 1.4 table 6.1. 10-bit adc0 electrical characteristics (c8051f022/3) vdd = 3.0v, av+ = 3.0v, vref = 2.40v (refbe=0), pga gain = 1, -40c to +85c unless otherwise specified parameter conditions min typ max units dc accuracy resolution 10 bits integral nonlinearity 1 lsb differential nonlinearity guaranteed monotonic 1 lsb offset error 0.5 lsb full scale error differential mode -1.50.5 lsb offset temperature coefficient 0.25 ppm/c dynamic performance (10 khz sine-wave input, 0 to 1 db below full scale, 100 ksps signal-to-noise plus distortion 59 db total harmonic distortion up to the 5 th harmonic -70 db spurious-free dynamic range 80 db conversion rate sar clock frequency 2.5 mhz conversion time in sar clocks 16 clocks track/hold acquisition time 1.5 s throughput rate 100 ksps analog inputs input voltage range single-ended operation 0 vref v *common-mode voltage range differential operation agnd av + v input capacitance 10 pf temperature sensor nonlinearity -1.0 +1.0 c absolute accuracy 3 c gain pga gain = 1 2.86 mv/c offset pga gain = 1, temp = 0c 0.776 v power specifications power supply current (av+ sup - plied to adc) operating mode, 100 ksps 450 900 a power supply rejection 0.3 mv/v
c8051f020/1/2/3 rev. 1.4 75 7. adc1 (8-bit adc) the adc1 subsystem for the c8051f020/1/2/3 consists of an 8-channel, configurable an alog multiplexer (amux1), a programmable gain amplifier (pga1), and a 500 ksps, 8-bit successive-approxima tion-register adc with inte - grated track-and-hold (see block diagram in figure 7.1 ). the amux1, pga1, and data conversion modes, are all configurable under software control via the special fu nction registers shown in figure 7.1 . the adc1 subsystem (8-bit adc, track-and-hold and pga) is enabled only when the ad1en bit in the adc1 control register (adc1cn) is set to logic 1. the adc1 subsystem is in low power shutdo wn when this bit is logic 0. the voltage reference used by adc1 is selected as described in section ?9. voltage reference (c8051f020/2)? on page 91 for c8051f020/2 devices, or section ?10. voltage reference (c8051f021/3)? on page 93 for c8051f021/3 devices. 7.1. analog multiplexer and pga eight adc1 channels are available for measuremen t, as selected by the amx1sl register (see figure 7.5 ). the pga amplifies the adc1 output signal by an amount determined by the states of the amp1gn2-0 bits in the adc1 con - figuration register, adc1cf ( figure 7.4 ). the pga can be software-programmed for gains of 0.5, 1, 2, or 4. gain defaults to 0.5 on reset. important note : ain1 pins also function as port 1 i/o pins, and must be configured as analog inputs when used as adc1 inputs. to configure an ain1 pin for analog input, set to ?0? the corresponding bit in register p1mdin. port 1 pins selected as analog inputs are skipped by the digital i/o crossbar. see section ?17.1.6. configuring port 1 pins as analog inputs (ain1.[7:0])? on page 165 for more information on configuring the ain1 pins. figure 7.1. adc1 functional block diagram 8-bit sar adc ref + - av+ 8 av+ ad1en sysclk x agnd adc1 adc1cf amp1gn0 amp1gn1 ad1sc0 ad1sc1 ad1sc2 ad1sc3 ad1sc4 amx1sl adc1cn ad1cm0 ad1cm1 ad1cm2 ad1busy ad1int ad1tm ad1en start conversion timer 3 overflow timer 2 overflow 000 001 010 011 write to ad1busy cnvstr 1xx write to ad0busy (synchronized with adc0) amx1ad0 amx1ad1 amx1ad2 8-to-1 amux ain1.0 (p1.0) ain1.1 (p1.1) ain1.2 (p1.2) ain1.3 (p1.3) ain1.4 (p1.4) ain1.5 (p1.5) ain1.6 (p1.6) ain1.7 (p1.7) ad1cm ad1cm
c8051f020/1/2/3 76 rev. 1.4 7.2. adc1 modes of operation adc1 has a maximum conversion speed of 500 ksps. the adc1 conversion clock (sar1 clock) is a divided version of the system clock, determined by the ad1sc bits in th e adc1cf register (system clock divided by (ad1sc + 1) for 0 ad1sc 31). the maximum adc1 conversion clock is 6 mhz. 7.2.1. starting a conversion a conversion can be initiated in one of five ways, dependi ng on the programmed states of the adc1 start of conver - sion mode bits (ad1cm2-0) in register adc1cn. conversions may be initiated by: 1. writing a ?1? to the ad1busy bit of adc1cn; 2. a timer 3 overflow (i.e. timed continuous conversions); 3. a rising edge detected on the external adc convert start signal, cnvstr; 4. a timer 2 overflow (i.e. timed continuous conversions); 5. writing a ?1? to the ad0busy of register adc0cn (initiate conversion of adc1 and adc0 with a single software command). during conversion, the ad1busy bit is set to logic 1 a nd restored to 0 when conversion is complete. the falling edge of ad1busy triggers an interrupt (when enabled) an d sets the interrupt flag in adc1cn. converted data is available in the adc1 data word, adc1. when a conversion is initiated by writing a ?1? to ad1busy, it is recommended to poll ad1int to determine when the conversion is complete. the recommended procedure is: step 1. write a ?0? to ad1int; step 2. write a ?1? to ad1busy; step 3. poll ad1int for ?1?; step 4. process adc1 data. 7.2.2. tracking modes the ad1tm bit in register adc1cn controls the adc1 track-and-hold mode. in its default state, the adc1 input is continuously tracked, except wh en a conversion is in progr ess. when the ad1tm bit is logic 1, adc1 operates in low-power track-and-hold mode. in this mode, each conversion is preceded by a tracking period of 3 sar clocks (after the start-of-conversion signal). when the cnvstr signal is used to initiate conversions in low-power tracking mode, adc1 tracks only when cnvstr is low; c onversion begins on the rising edge of cnvstr (see figure 7.2 ). tracking can also be disabled (shutdow n) when the entire chip is in low po wer standby or sleep modes. low-power track-and-hold mode is also useful when amux or pga set tings are frequently changed, due to the settling time requirements described in section ?7.2.3. settling time requirements? on page 78 .
c8051f020/1/2/3 rev. 1.4 77 figure 7.2. adc1 track and conversion example timing write '1' to ad1busy, timer 3 overflow, timer 2 overflow, write '1' to ad0busy (ad1cm[2:0]=000, 001, 011, 1xx) ad1tm=1 ad1tm=0 sar1 clocks 123456789101112 123456789 sar1 clocks track convert low power mode low power or convert track or convert convert track b. adc timing for internal trigger source 123456789 cnvstr (ad1cm[2:0]=010) ad1tm=1 a. adc timing for external trigger source sar1 clocks track or convert convert track ad1tm=0 track convert low power mode low power or convert
c8051f020/1/2/3 78 rev. 1.4 7.2.3. settling time requirements when the adc1 input configuration is changed (i.e., a di fferent mux or pga selecti on), a minimum settling (or tracking) time is required before an accurate conversion can be pe rformed. this settling time is determined by the adc1 mux resistance, the adc1 sampling capacitance, any external source resi stance, and the accuracy required for the conversion. figure 7.3 shows the equivalent adc1 input circuit. the required adc1 settling time for a given settling accuracy (sa) may be approximated by equation 7.1 . note that in low-power tracking mode, three sar1 clocks are used for tracking at the star t of every conversion. for most applicat ions, these three sar1 clocks will meet the tracking requirements. see table 7.1 for absolute minimum settling time requirements. where: sa is the settling accuracy, given as a fraction of an ls b (for example, 0.25 to settle within 1/4 lsb) t is the required tracking time in seconds r total is the sum of the adc1 mux resistan ce and any external source resistance. n is the adc resolution in bits (8). equation 7.1. adc1 settling time requirements t 2 n sa ------ - ?? ?? r total c sample ln = r mux = 5k c sample = 10pf rc input = r mux * c sample mux select ain1.x figure 7.3. adc1 equivalent input circuit
c8051f020/1/2/3 rev. 1.4 79 figure 7.4. adc1cf: adc1 config uration register (c8051f020/1/2/3) bits7-3: ad1sc4-0: adc1 sar conversion clock period bits sar conversion clock is derived from system clock by the following equation, where ad1sc refers to the 5-bit value held in ad1sc4-0. sar conversion clock requirements are given in table 7.1. bit2: unused. read = 0b. write = don?t care. bits1-0: amp1gn1-0: adc1 internal amplifier gain (pga) 00: gain = 0.5 01: gain = 1 10: gain = 2 11: gain = 4 r/w r/w r/w r/w r/w r/w r/w r/w reset value ad1sc4 ad1sc3 ad1sc2 ad1sc1 ad1sc0 - amp1gn1 amp1gn0 11111000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xab a d 1 sc sysclk clk sar 1 ------------ ---------- -1 ? = figure 7.5. amx1sl: amux1 channe l select register (c8051f020/1/2/3) bits7-3: unused. read = 00000b; write = don?t care bits2-0: amx1ad2-0: amx1 address bits 000-111b: adc1 inputs selected as follows: 000: ain1.0 selected 001: ain1.1 selected 010: ain1.2 selected 011: ain1.3 selected 100: ain1.4 selected 101: ain1.5 selected 110: ain1.6 selected 111: ain1.7 selected r/w r/w r/w r/w r/w r/w r/w r/w reset value - - - - - amx1ad2 amx1ad1 amx1ad0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xac
c8051f020/1/2/3 80 rev. 1.4 figure 7.6. adc1cn: adc1 cont rol register (c8051f020/1/2/3) bit7: ad1en: adc1 enable bit. 0: adc1 disabled. adc1 is in low-power shutdown. 1: adc1 enabled. adc1 is active and ready for data conversions. bit6: ad1tm: adc1 track mode bit. 0: normal track mode: when adc1 is enabled, track ing is continuous unless a conversion is in pro- cess. 1: low-power track mode: tracking defined by ad1stm2-0 bits (see below). bit5: ad1int: adc1 conversion complete interrupt flag. this flag must be cleared by software. 0: adc1 has not completed a data conversion since the last time this flag was cleared. 1: adc1 has completed a data conversion. bit4: ad1busy: adc1 busy bit. read: 0: adc1 conversion is complete or a conversion is not currently in progress. ad1int is set to logic 1 on the falling edge of ad1busy. 1: adc1 conversion is in progress. write: 0: no effect. 1: initiates adc1 conversion if ad1stm2-0 = 000b bit3-1: ad1cm2-0: adc1 start of conversion mode select. ad1tm = 0: 000: adc1 conversion initiated on every write of ?1? to ad1busy. 001: adc1 conversion initiated on overflow of timer 3. 010: adc1 conversion initiated on rising edge of external cnvstr. 011: adc1 conversion initiated on overflow of timer 2. 1xx: adc1 conversion initiated on write of ?1? to ad0busy (synchronized with adc0 software- commanded conversions). ad1tm = 1: 000: tracking initiated on write of ?1? to ad1busy and lasts 3 sar1 clocks, followed by conver- sion. 001: tracking initiated on overflow of timer 3 and lasts 3 sar1 clocks, followed by conversion. 010: adc1 tracks only when cnvstr input is logic low; conversion starts on rising cnvstr edge. 011: tracking initiated on overflow of timer 2 and lasts 3 sar1 clocks, followed by conversion. 1xx: tracking initiated on write of ?1? to ad0busy and lasts 3 sar1 clocks, followed by conver- sion. bit0: unused. read = 0b. write = don?t care. r/w r/w r/w r/w r/w r/w r/w r/w reset value ad1en ad1tm ad1int ad1busy ad1cm2 ad1cm1 ad1cm0 - 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xaa
c8051f020/1/2/3 rev. 1.4 81 figure 7.7. adc1: adc1 data word register bits7-0: adc1 data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x9c figure 7.8. adc1 data word example 8-bit adc data word appears in the adc1 data word register as follows: example: adc1 data word conversion map, ain1.0 input (amx1sl = 0x00) ain1.0-agnd (volts) adc1 vref * (255/256) 0xff vref / 2 0x80 vref * (127/256) 0x7f 00x00 code vin gain vref --------------- 256 =
c8051f020/1/2/3 82 rev. 1.4 table 7.1. adc1 electrical characteristics vdd = 3.0 v, av + = 3 . 0 v, vref1 = 2.40 v (refbe=0), pga1 = 1, -40c to +85c unless otherwise specified parameter conditions min typ max units dc accuracy resolution 8 bits integral nonlinearity 1 lsb differential nonlinearity guaranteed monotonic 1 lsb offset error 0.50.3 lsb full scale error differential mode -10.2 lsb offset temperature coefficient tbd ppm/c dynamic performance (10 khz sine-wave input, 0 to 1 db below full scale, 500 ksps signal-to-noise plus distortion 45 47 db total harmonic distortion up to the 5 th harmonic -51 db spurious-free dynamic range 52 db conversion rate sar conversion clock 6 mhz conversion time in sar clocks 8 clocks track/hold acquisition time 300 ns throughput rate 500 ksps analog inputs input voltage range 0 vref v input capacitance 10 pf power specifications power supply current (av+ sup - plied to adc1) operating mode, 500 ksps 420 900 a power supply rejection 0.3 mv/v
c8051f020/1/2/3 rev. 1.4 83 8. dacs, 12-bit voltage mode each c8051f020/1/2/3 device includes two on-chip 12-bit voltage-mode digital-to-analog converters (dacs). each dac has an output swing of 0v to (vref-1lsb) fo r a corresponding input code range of 0x000 to 0xfff. the dacs may be enabled/disabled via their corresponding co ntrol registers, dac0cn and dac1cn. while disabled, the dac output is maintained in a high-impedan ce state, and the dac supply current falls to 1 a or less. the volt - age reference for each dac is supplied at the vrefd pin (c8051f020/2 devices) or the vref pin (c8051f021/3 devices). note that the vref pin on c8051f021/3 devices may be driven by the internal voltage reference or an external source. if the internal voltage reference is used it must be enabled in order for the dac outputs to be valid. see section ?9. voltage reference (c8051f020/2)? on page 91 or section ?10. voltage refer - ence (c8051f021/3)? on page 93 for more information on configuring the voltage reference for the dacs. 8.1. dac output scheduling each dac features a flexible output update mechanism which allows for s eamless full-scale changes and supports jitter-free updates for waveform generation. the followin g examples are written in te rms of dac0, but dac1 opera - tion is identical. note that r eads from dac0l return pre-latch data, meani ng the value read is the same as the last value written to this register, not the value at the dac0l latch. reads from dac0h always return the value at the dac0h latch. dac0 av+ 12 agnd 8 8 ref dac0 dac0cn dac0en dac0md1 dac0md0 dac0df2 dac0df1 dac0df0 dac0h dac0l dig. mux latch latch 8 8 dac1 av+ 12 agnd 8 8 ref dac1 dac1cn dac1en dac1md1 dac1md0 dac1df2 dac1df1 dac1df0 dac1h dac1l dig. mux latch latch 8 8 dac0h timer 3 timer 4 timer 2 dac1h timer 3 timer 4 timer 2 figure 8.1. dac functional block diagram
c8051f020/1/2/3 84 rev. 1.4 8.1.1. update output on-demand in its default mode (dac0cn.[4:3] = ?00?) the dac0 output is updated ?on-demand? on a write to the high-byte of the dac0 data register (dac0h). it?s important to note that writes to dac0l are held , and have no effect on the dac0 output until a write to dac0h takes pl ace. if writing a full 12-bi t word to the dac data registers, the 12-bit data word is written to the low byte (dac0l) and high byte (dac0h) data registers. data is latched into dac0 after a write to the corresponding dac0h register, so the write sequence should be dac0l followed by dac0h if the full 12-bit resolution is required. the dac can be used in 8-bit mode by initializing dac0l to the desired value (typ - ically 0x00), and writing data to only dac0h (also see section 8.2 for information on formatting the 12-bit dac data word within the 16-bit sfr space). 8.1.2. update output based on timer overflow similar to the adc operation, in which an adc conversion can be initiated by a timer overflow independently of the processor, the dac outputs can use a timer overflow to schedu le an output update event. this feature is useful in systems where the dac is used to genera te a waveform of a defined sampling rate by eliminating the effects of vari - able interrupt latency and instruction execution on the timing of the dac output. when the dac0md bits (dac0cn.[4:3]) are set to ?01?, ?10?, or ?11?, writes to both dac data registers (dac0l and dac0h) are held until an associated timer overflow event (timer 3, timer 4, or timer 2, respectively) occurs, at which time the dac0h:dac0l contents are copied to the dac input latches allowing the dac output to change to the new value. 8.2. dac output scal ing/justification in some instances, input data should be shifted prior to a dac0 write operation to properly justify data within the dac input registers. this action would typically require one or more load and shift operations, adding software over - head and slowing dac throughput. to alleviate this problem, the data-formatting feature provides a means for the user to program the orientation of the dac0 data word within data registers dac0h and dac0l. the three dac0df bits (dac0cn.[2:0]) allow the us er to specify one of five data word orientations as shown in the dac0cn register definition. dac1 is functionally the same as dac0 described above. the electrical specifications for both dac0 and dac1 are given in table 8.1 .
c8051f020/1/2/3 rev. 1.4 85 figure 8.2. dac0h: dac0 high byte register bits7-0: dac0 data word most significant byte. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xd3 figure 8.3. dac0l: dac0 low byte register bits7-0: dac0 data word least significant byte. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xd2
c8051f020/1/2/3 86 rev. 1.4 figure 8.4. dac0cn: dac0 control register bit7: dac0en: dac0 enable bit. 0: dac0 disabled. dac0 output pin is disabled; dac0 is in low-power shutdown mode. 1: dac0 enabled. dac0 output pin is active; dac0 is operational. bits6-5: unused. read = 00b; write = don?t care. bits4-3: dac0md1-0: dac0 mode bits. 00: dac output updates occur on a write to dac0h. 01: dac output updates occur on timer 3 overflow. 10: dac output updates occur on timer 4 overflow. 11: dac output updates occur on timer 2 overflow. bits2-0: dac0df2-0: dac0 data format bits: 000: the most significant nibble of the dac0 data word is in dac0h[3:0], while the least significant byte is in dac0l. 001: the most significant 5-bits of the dac0 data word is in dac0h[4:0], while the least significant 7-bits are in dac0l[7:1]. 010: the most significant 6-bits of the dac0 data word is in dac0h[5:0], while the least significant 6-bits are in dac0l[7:2]. 011: the most significant 7-bits of the dac0 data word is in dac0h[6:0], while the least significant 5-bits are in dac0l[7:3]. 1xx: the most significant 8-bits of the dac0 data word is in dac0h[7:0], while the least significant 4-bits are in dac0l[7:4]. r/w r/w r/w r/w r/w r/w r/w r/w reset value dac0en - - dac0md1 dac0md0 dac0df2 dac0df1 dac0df0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xd4 dac0h dac0l msb lsb dac0h dac0l msb lsb dac0h dac0l msb lsb dac0h dac0l msb lsb dac0h dac0l msb lsb
c8051f020/1/2/3 rev. 1.4 87 figure 8.5. dac1h: dac1 high byte register bits7-0: dac1 data word most significant byte. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xd6 figure 8.6. dac1l: dac1 low byte register bits7-0: dac1 data word least significant byte. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xd5
c8051f020/1/2/3 88 rev. 1.4 figure 8.7. dac1cn: dac1 control register bit7: dac1en: dac1 enable bit. 0: dac1 disabled. dac1 output pin is disabled; dac1 is in low-power shutdown mode. 1: dac1 enabled. dac1 output pin is active; dac1 is operational. bits6-5: unused. read = 00b; write = don?t care. bits4-3: dac1md1-0: dac1 mode bits: 00: dac output updates occur on a write to dac1h. 01: dac output updates occur on timer 3 overflow. 10: dac output updates occur on timer 4 overflow. 11: dac output updates occur on timer 2 overflow. bits2-0: dac1df2: dac1 data format bits: 000: the most significant nibble of the dac1 data word is in dac1h[3:0], while the least significant byte is in dac1l. 001: the most significant 5-bits of the dac1 data word is in dac1h[4:0], while the least significant 7-bits are in dac1l[7:1]. 010: the most significant 6-bits of the dac1 data word is in dac1h[5:0], while the least significant 6-bits are in dac1l[7:2]. 011: the most significant 7-bits of the dac1 data word is in dac1h[6:0], while the least significant 5-bits are in dac1l[7:3]. 1xx: the most significant 8-bits of the dac1 data word is in dac1h[7:0], while the least significant 4-bits are in dac1l[7:4]. r/w r/w r/w r/w r/w r/w r/w r/w reset value dac1en - - dac1md1 dac1md0 dac1df2 dac1df1 dac1df0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xd7 dac1h dac1l msb lsb dac1h dac1l msb lsb dac1h dac1l msb lsb dac1h dac1l msb lsb dac1h dac1l msb lsb
c8051f020/1/2/3 rev. 1.4 89 table 8.1. dac electrical characteristics vdd = 3.0 v, av + = 3 . 0 v, vref = 2.40 v (refbe = 0), no output load unless otherwise specified parameter conditions min typ max units static performance resolution 12 bits integral nonlinearity 2 lsb differential nonlinearity 1 lsb output noise no output filter 100 khz output filter 10 khz output filter 250 128 41 vrms offset error data word = 0x014 3 30 mv offset tempco 6 ppm/c gain error 20 60 mv gain-error tempco 10 ppm/c vdd power supply rejection ratio -60 db output impedance in shutdown mode dacnen = 0 100 k ? output sink current 300 a output short-circuit current data word = 0xfff 15 ma dynamic performance voltage output slew rate load = 40pf 0.44 v/s output settling time to 1/2 lsb load = 40pf, output swing from code 0xfff to 0x014 10 s output voltage swing 0 vref- 1lsb v startup time 10 s analog outputs load regulation i l = 0.01ma to 0.3ma at code 0xfff 60 ppm power consumption (each dac) power supply current (av+ sup - plied to dac) data word = 0x7ff 110 400 a
c8051f020/1/2/3 90 rev. 1.4 notes
c8051f020/1/2/3 rev. 1.4 91 9. voltage reference (c8051f020/2) the voltage reference circuit offers full flexibility in operating the adc and dac modules. three voltage reference input pins allow each adc and the two dacs to reference an external voltage reference or the on-chip voltage refer - ence output. adc0 may also reference th e dac0 output internally, and adc1 may reference the analog power sup - ply voltage, via the vref multiplexers shown in figure 9.1 . the internal voltage referen ce circuit consists of a 1.2 v, 1 5 ppm/c (typical) bandgap voltage reference generator and a gain-of-two output buffer amplifier. the internal refe rence may be routed via the vr ef pin to external system components or to the voltage reference input pins shown in figure 9.1 . bypass capacitors of 0.1 f and 4.7 f are recommended from the vref pin to agnd, as shown in figure 9.1 . see table 9.1 for voltage reference specifica - tions. the reference control register, ref0cn (defined in figure 9.2 ) enables/disables the internal reference generator and selects the reference inputs for adc0 and adc1. the biase bit in ref0cn enables the on-board reference generator while the refbe bit enables the gain-of-two buffe r amplifier which drives the vref pin. when disabled, the supply current drawn by the bandgap and buffer amplifier falls to less than 1 a (typical) and the output of the buffer amplifier enters a high impedance state. if the internal bandgap is used as the reference voltage generator, biase and refbe must both be set to logic 1. if the internal reference is not used, refbe may be set to logic 0. note that the biase bit must be set to logic 1 if either dac or adc is used, regardless of whether the voltage refer - ence is derived from the on-chip reference or supplied by an off-chip source. if neither the adc nor the dac are being used, both of these bits can be set to logic 0 to c onserve power. bits ad0vrs and ad1vrs select the adc0 and adc1 voltage reference sources, resp ectively. the electrical specifications for the voltage reference circuit are given in table 9.1 . recommended bypass capacitors x2 vref dac0 dac1 ref vrefd av+ adc1 adc0 vref1 ref ref 1 0 0 1 vref0 4.7 f0.1 f external voltage reference circuit r1 vdd dgnd ref0cn refbe biase tempe ad1vrs ad0vrs refbe biase bias to adcs, dacs 1.2v band-gap en figure 9.1. voltage referenc e functional block diagram
c8051f020/1/2/3 92 rev. 1.4 the temperature sensor connects to the highest order input of the adc0 input multiplexer (see section ?5.1. analog multiplexer and pga? on page 43 for c8051f020/1 devices, or section ?6.1. analog multiplexer and pga? on page 59 for c8051f022/3 devices). the tempe bit within ref0 cn enables and disables the temperature sensor. while disabled, the temperature sensor defaults to a high impedance state and any a/d measurements performed on the sensor while disabled result in undefined data. table 9.1. voltage reference electrical characteristics vdd = 3.0 v, av + = 3 . 0 v, -40c to +85c unless otherwise specified parameter conditions min typ max units internal reference (refbe = 1) output voltage 25c ambient 2.36 2.43 2.48 v vref short-circuit current 30 ma vref temperature coefficient 15 ppm/c load regulation load = 0 to 200 a to agnd 0.5 ppm/a vref turn-on time 1 4.7f tantalum, 0.1f ceramic bypass 2 ms vref turn-on time 2 0.1f ceramic bypass 20 s vref turn-on time 3 no bypass cap 10 s external reference (refbe = 0) input voltage range 1.00 (av+) - 0.3 v input current 0 1 a figure 9.2. ref0cn: reference control register bits7-5: unused. read = 000b; write = don?t care. bit4: ad0vrs: adc0 voltage reference select 0: adc0 voltage reference from vref0 pin. 1: adc0 voltage reference from dac0 output. bit3: ad1vrs: adc1 voltage reference select 0: adc1 voltage reference from vref1 pin. 1: adc1 voltage reference from av+. bit2: tempe: temperature sensor enable bit. 0: internal temperature sensor off. 1: internal temper ature sensor on. bit1: biase: adc/dac bias generator enable bit. (must be ?1? if using adc or dac). 0: internal bias generator off. 1: internal bias generator on. bit0: refbe: internal reference buffer enable bit. 0: internal reference buffer off. 1: internal reference buffer on. internal voltage reference is driven on the vref pin. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - - ad0vrs ad1vrs tempe biase refbe 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xd1
c8051f020/1/2/3 rev. 1.4 93 10. voltage refere nce (c8051f021/3) the internal voltage referen ce circuit consists of a 1.2 v, 1 5 ppm/c (typical) bandgap voltage reference generator and a gain-of-two output buffer amplifier. the internal refe rence may be routed via the vr ef pin to external system components or to the vrefa input pin shown in figure 10.1 . bypass capacitors of 0.1 f and 4.7 f are recom - mended from the vref pin to agnd, as shown in figure 10.1 . see table 10.1 for voltage reference specifications. the vrefa pin provides a voltage reference input for adc0 and adc1. adc0 may also reference the dac0 out - put internally, and adc1 may reference the analog power supply voltage, via the vref multiplexers shown in figure 10.1 . the reference control regist er, ref0cn (defined in figure 10.2 ) enables/disables the internal reference generator and selects the reference inputs for adc0 and adc1. the biase bit in ref0cn enables the on-board reference generator while the refbe bit enables the gain-of-two buffe r amplifier which drives the vref pin. when disabled, the supply current drawn by the bandgap and buffer amplifier falls to less than 1 a (typical) and the output of the buffer amplifier enters a high impedance state. if the internal bandgap is used as the reference voltage generator, biase and refbe must both be set to 1 (this includes any tim e a dac is used). if the inte rnal reference is not used, refbe may be set to logic 0. note that the biase bit must be set to logic 1 if either adc is used, regardless of whether the voltage reference is derived from the on-chip re ference or supplied by an off-chip source. if neither the adc nor the dac are being used, both of these bits can be set to logic 0 to conserve power. bits ad0vrs and ad1vrs select the adc0 and adc1 voltage reference source s, respectively. the electri cal specifications for the voltage reference are given in table 10.1 . recommended bypass capacitors x2 vref dac0 dac1 ref av+ adc1 adc0 ref ref 1 0 0 1 vrefa 4.7 f0.1 f external voltage reference circuit r1 vdd dgnd ref0cn refbe biase tempe ad1vrs ad0vrs refbe biase bias to adcs, dacs 1.2v band-gap en figure 10.1. voltage reference functional block diagram
c8051f020/1/2/3 94 rev. 1.4 the temperature sensor connects to the highest order input of the adc0 input multiplexer (see section ?5.1. analog multiplexer and pga? on page 43 for c8051f020/1 devices, or section ?6.1. analog multiplexer and pga? on page 59 for c8051f022/3 devices). the tempe bit within ref0 cn enables and disables the temperature sensor. while disabled, the temperature sensor defaults to a high impedance state and any a/d measurements performed on the sensor while disabled result in undefined data . table 10.1. voltage reference electrical characteristics vdd = 3.0 v, av + = 3 . 0 v, -40c to +85c unless otherwise specified parameter conditions min typ max units internal reference (refbe = 1) output voltage 25c ambient 2.36 2.43 2.48 v vref short-circuit current 30 ma vref temperature coefficient 15 ppm/c load regulation load = 0 to 200 a to agnd 0.5 ppm/a vref turn-on time 1 4.7f tantalum, 0.1f ceramic bypass 2 ms vref turn-on time 2 0.1f ceramic bypass 20 s vref turn-on time 3 no bypass cap 10 s external reference (refbe = 0) input voltage range 1.00 (av+) - 0.3 v input current 0 1 a figure 10.2. ref0cn: reference control register bits7-5: unused. read = 000b; write = don?t care. bit4: ad0vrs: adc0 voltage reference select 0: adc0 voltage reference from vrefa pin. 1: adc0 voltage reference from dac0 output. bit3: ad1vrs: adc1 voltage reference select 0: adc1 voltage reference from vrefa pin. 1: adc1 voltage reference from av+. bit2: tempe: temperature sensor enable bit. 0: internal temperature sensor off. 1: internal temper ature sensor on. bit1: biase: adc/dac bias generator enable bit. (must be ?1? if using adc or dac). 0: internal bias generator off. 1: internal bias generator on. bit0: refbe: internal reference buffer enable bit. 0: internal reference buffer off. 1: internal reference buffer on. internal voltage reference is driven on the vref pin. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - - ad0vrs ad1vrs tempe biase refbe 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xd1
c8051f020/1/2/3 rev. 1.4 95 11. comparators each mcu includes two on-board voltage comparators as shown in figure 11.1 . the inputs of each comparator are available at the package pins. the output of each comparator is optionally ava ilable at the packag e pins via the i/o crossbar. when assigned to package pi ns, each comparator output can be pr ogrammed to operate in open drain or push-pull modes. see section ?17. port input/output? on page 161 for crossbar and port initialization details. the hysteresis of each compar ator is software-programmable via its resp ective comparator control register (cpt0cn and cpt1cn for comparator0 and comparator1, respectively). the user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive an d negative-going symmetry of this hysteresis around the threshold voltage. the output of the comparator can be polled in software, or can be used as an interrupt source. each comparator can be individually enabled or disabled (shutdow n). when disabled, the comparat or output (if assigned to a port i/o pin via the crossbar) defaults to the logic low st ate, its interrupt capability is suspended and its supply cur - rent falls to less than 1 a. comparator inputs can be externally driven from -0.25 v to (av+) + 0.25 v without dam - age or upset. the comparator0 hysteresis is programmed using bits 3-0 in the comparator0 control register cpt0cn (shown in figure 11.1 ). the amount of negative hysteresis voltage is determined by the settings of the cp0hyn bits; in a simi - lar way, the amount of positive hysteresis is determined by the setting the cp0hyp bits. see table 11.1 on page 99 for hysteresis level specifications. comparator interrupts can be generated on rising-edge and/or falling-edge output transitions. (for interrupt enable and priority control, see section ?12.3. interrupt handler? on page 116 ). the cp0fif flag is set upon a comparator0 falling-edge interrupt, and the cp0rif flag is set upon the comparator0 ri sing-edge interrupt. once set, these bits remain set until cleared by software. the output state of comparator0 can be obtained at any time by read - ing the cp0out bit. comparator0 is enabled by setting the cp0en bit to logic 1, and is disabled by clearing this bit + - av+ q q set clr d q q set clr d crossbar interrupt handler reset decision tree (synchronizer) cp0+ cp0- agnd cpt0cn cp0en cp0out cp0rif cp0fif cp0hyp1 cp0hyp0 cp0hyn1 cp0hyn0 + - av+ q q set clr d q q set clr d crossbar interrupt handler (synchronizer) cp1+ cp1- agnd cpt1cn cp1en cp1out cp1rif cp1fif cp1hyp1 cp1hyp0 cp1hyn1 cp1hyn0 figure 11.1. comparator functional block diagram
c8051f020/1/2/3 96 rev. 1.4 to logic 0. comparat or0 can also be programmed as a reset source; for details, see section ? 13.6. comparator0 reset ? on page 129 . the operation of comparator1 is identical to that of comparator0, thoug h comparator1 may not be configured as a reset source. comparator1 is controlled by the cpt1cn register ( figure 11.4 ). the complete electrical specifications for the comparators are given in table 11.1 . positive hysteresis voltage (programmed with cp0hyp bits) negative hysteresis voltage (programmed by cp0hyn bits) vin- vin+ inputs circuit configuration + _ cp0+ cp0- cp0 vin+ vin- out v oh positive hysteresis disabled maximum positive hysteresis negative hysteresis disabled maximum negative hysteresis output v ol figure 11.2. comparator hysteresis plot
c8051f020/1/2/3 rev. 1.4 97 figure 11.3. cpt0cn: comparator0 control register bit7: cp0en: comparator0 enable bit. 0: comparator0 disabled. 1: comparator0 enabled. bit6: cp0out: comparator 0 output state flag. 0: voltage on cp0+ < cp0-. 1: voltage on cp0+ > cp0-. bit5: cp0rif: comparator0 rising-edge interrupt flag. 0: no comparator0 rising edge interrupt has occurred since this fl ag was last cleared. 1: comparator0 rising edge interrupt has occurred. bit4: cp0fif: comparator0 falling-edge interrupt flag. 0: no comparator0 falling-edge interrupt has occurred since this flag was last cleared. 1: comparator0 falling-edge interrupt has occurred. bits3-2: cp0hyp1-0: comparator0 po sitive hysteresis control bits. 00: positive hysteresis disabled. 01: positive hysteresis = 2 mv. 10: positive hysteresis = 4 mv. 11: positive hysteresis = 10 mv. bits1-0: cp0hyn1-0: comparator0 negative hysteresis control bits. 00: negative hysteresis disabled. 01: negative hysteresis = 2 mv. 10: negative hysteresis = 4 mv. 11: negative hysteresis = 10 mv. r/w r/w r/w r/w r/w r/w r/w r/w reset value cp0en cp0out cp0rif cp0fif cp0hyp1 cp0hyp0 cp0hyn1 cp0hyn0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x9e
c8051f020/1/2/3 98 rev. 1.4 figure 11.4. cpt1cn: comparator1 control register bit7: cp1en: comparator1 enable bit. 0: comparator1 disabled. 1: comparator1 enabled. bit6: cp1out: comparator 1 output state flag. 0: voltage on cp1+ < cp1-. 1: voltage on cp1+ > cp1-. bit5: cp1rif: comparator1 rising-edge interrupt flag. 0: no comparator1 rising edge interrupt has occurred since this fl ag was last cleared. 1: comparator1 rising edge interrupt has occurred. bit4: cp1fif: comparator1 falling-edge interrupt flag. 0: no comparator1 falling-edge interrupt has occurred since this flag was last cleared. 1: comparator1 falling-edge interrupt has occurred. bits3-2: cp1hyp1-0: comparator1 po sitive hysteresis control bits. 00: positive hysteresis disabled. 01: positive hysteresis = 2 mv. 10: positive hysteresis = 4 mv. 11: positive hysteresis = 10 mv. bits1-0: cp1hyn1-0: comparator1 negative hysteresis control bits. 00: negative hysteresis disabled. 01: negative hysteresis = 2 mv. 10: negative hysteresis = 4 mv. 11: negative hysteresis = 10 mv. r/w r/w r/w r/w r/w r/w r/w r/w reset value cp1en cp1out cp1rif cp1fif cp1hyp1 cp1hyp0 cp1hyn1 cp1hyn0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x9f
c8051f020/1/2/3 rev. 1.4 99 table 11.1. comparator electrical characteristics vdd = 3.0 v, av + = 3 . 0 v, -40c to +85c unless otherwise specified parameter conditions min typ max units response time 1 cp+ - cp- = 100 mv 4 s response time 2 cp+ - cp- = 10 mv 12 s common-mode rejection ratio 1.5 4 mv/v positive hysteresis 1 cpnhyp1-0 = 00 0 1 mv positive hysteresis 2 cpnhyp1-0 = 01 2 4.5 7 mv positive hysteresis 3 cpnhyp1-0 = 10 4 9 13 mv positive hysteresis 4 cpnhyp1-0 = 11 10 17 25 mv negative hysteresis 1 cpnhyn1-0 = 00 0 1 mv negative hysteresis 2 cpnhyn1-0 = 01 2 4.5 7 mv negative hysteresis 3 cpnhyn1-0 = 10 4 9 13 mv negative hysteresis 4 cpnhyn1-0 = 11 10 17 25 mv inverting or non-inverting input voltage range -0.25 (av+) + 0.25 v input capacitance 7 pf input bias current -5 0.001 +5 na input offset voltage -10 +10 mv power supply power-up time cpnen from 0 to 1 20 s power supply rejection 0.1 1 mv/v supply current operating mode (each comparator) at dc 1.5 10 a
c8051f020/1/2/3 100 rev. 1.4 notes
c8051f020/1/2/3 rev. 1.4 101 12. cip-51 microcontroller the mcu system controller core is th e cip-51 microcontroller. the cip-51 is fully compatible with the mcs-51? instruction set; standard 803x/805x assemblers and compilers can be used to develop software. the mcu family has a superset of all the peripherals includ ed with a standard 8051. included are five 16-bit counter/timers (see descrip - tion in section 22 ), two full-duplex uarts (see description in section 20 and section 21 ), 256 bytes of internal ram, 128 byte special function regist er (sfr) address space (see section 12.2.6 ), and 8/4 byte-wide i/o ports (see description in section 17 ). the cip-51 also includes on-chip debug hardware (see description in section 24 ), and interfaces directly with the mcus' anal og and digital subsystems providing a complete data acquisition or control- system solution in a single integrated circuit. the cip-51 microcontroller core implemen ts the standard 8051 organization and peripherals as well as additional custom peripherals and functions to extend its capability (see figure 12.1 for a block diagram). the cip-51 includes the following features: data bus tmp1 tmp2 prgm. address reg. pc incrementer alu psw data bus data bus memory interface mem_address d8 pipeline buffer data pointer interrupt interface system_irqs emulation_irq mem_control control logic a16 program counter (pc) stop clock reset idle power control register data bus sfr bus interface sfr_address sfr_control sfr_write_data sfr_read_data d8 d8 b register d8 d8 accumulator d8 d8 d8 d8 d8 d8 d8 d8 mem_write_data mem_read_data d8 sram address register sram (256 x 8) d8 stack pointer d8 figure 12.1. cip-51 block diagram - fully compatible with mcs-51 instruction set - 25 mips peak throughput with 25 mhz clock - 0 to 25 mhz clock frequency - 256 bytes of internal ram - 8/4 byte-wide i/o ports - extended interrupt handler - reset input - power management modes - on-chip debug logic - program and data memory security
c8051f020/1/2/3 102 rev. 1.4 performance the cip-51 employs a pipelined architectur e that greatly increases its instruct ion throughput over the standard 8051 architecture. in a standard 8051, all instructions except for mul and div take 12 or 24 system clock cycles to exe - cute, and usually have a maximum system clock of 12 mhz. by contrast, the cip-51 core executes 70% of its instruc - tions in one or two system clock cycles, with no inst ructions taking more than eight system clock cycles. with the cip-51's maxi mum system clock at 25 mhz, it has a peak throughput of 25 mips. the cip-51 has a total of 109 instructions. the table below shows the total nu mber of instructions that require each execution time. programming and debugging support a jtag-based serial interface is provided for in-syste m programming of the flash program memory and commu - nication with on-chip debug support logic. the re-programmable flash can also be read and changed a single byte at a time by the application software using the movc and movx instructions. this feature allows program memory to be used for non-volatile data storage as well as updating program code under software control. the on-chip debug support logic facilitates full speed in-c ircuit debugging, allowing the setting of hardware break - points and watch points, starting, stopping and single stepping through program execution (including interrupt service routines), examination of the program's call stack, and reading/wr iting the contents of registers and memory. this method of on-chip debug is completely non-intrusive and non-invasive, requiring no ram, stack, timers, or other on-chip resources. the cip-51 is supported by development tools from silicon labs and third party vendors. silicon labs provides an integrated development environment (ide) including edit or, macro assembler, debugger and programmer. the ide's debugger and programmer interface to th e cip-51 via its jtag interface to prov ide fast and efficient in-system device programming and debugging. third party macro assemblers and c compilers are also available. 12.1. instruction set the instruction set of the cip-51 system controller is fully compatible with the standard mcs-51? instruction set; standard 8051 development tools can be used to develop software for the cip-51. all cip-51 instructions are the binary and functional equivalent of their mcs-51? counterparts, including opcodes, addressing modes and effect on psw flags. however, instruction timing is different than that of the standard 8051. 12.1.1. instruction and cpu timing in many 8051 implementations, a distinction is made between machine cycles and clock cycles, with machine cycles varying from 2 to 12 clock cycles in length. however, the cip-51 imp lementation is based solely on clock cycle tim - ing. all instruction timings are specified in terms of clock cycles. due to the pipelined architectur e of the cip-51, most instructions execute in the same number of clock cycles as there are program bytes in the instruction. conditional branch inst ructions take one less clock cycle to complete when the branch is not taken as opposed to when the branch is taken. table 12.1 is the cip-51 instruction set summary , which includes the mnemonic, number of bytes, and number of clock cycles for each instruction. 12.1.2. movx instruction and program memory in the cip-51, the movx instructi on serves three purposes: accessing on- chip xram, accessing off-chip xram, and accessing on-chip program flash memo ry. the flash access feature provides a mechanism for user software to update program code and use the program memory space for non-volatile data storage (see section ?15. flash clocks to execute 1 2 2/3 3 3/4 4 4/5 5 8 number of instructions 26 50 5 14 7 3 1 2 1
c8051f020/1/2/3 rev. 1.4 103 memory? on page 139 ). the external memory interface provides a fast access to off-chip xram (or memory- mapped peripherals) via the movx instruction. refer to section ?16. external data memory inter - face and on-chip xram? on page 145 for details. table 12.1. cip-51 instruction set summary mnemonic description bytes clock cycles arithmetic operations add a, rn add register to a 1 1 add a, direct add direct byte to a 2 2 add a, @ri add indirect ram to a 1 2 add a, #data add immediate to a 2 2 addc a, rn add register to a with carry 1 1 addc a, direct add direct byte to a with carry 2 2 addc a, @ri add indirect ram to a with carry 1 2 addc a, #data add immediate to a with carry 2 2 subb a, rn subtract register from a with borrow 1 1 subb a, direct subtract direct byte from a with borrow 2 2 subb a, @ri subtract indirect ram from a with borrow 1 2 subb a, #data subtract immediate from a with borrow 2 2 inc a increment a 1 1 inc rn increment register 1 1 inc direct increment direct byte 2 2 inc @ri increment indirect ram 1 2 dec a decrement a 1 1 dec rn decrement register 1 1 dec direct decrement direct byte 2 2 dec @ri decrement indirect ram 1 2 inc dptr increment data pointer 1 1 mul ab multiply a and b 1 4 div ab divide a by b 1 8 da a decimal adjust a 1 1 logical operations anl a, rn and register to a 1 1 anl a, direct and direct byte to a 2 2 anl a, @ri and indirect ram to a 1 2 anl a, #data and immediate to a 2 2 anl direct, a and a to direct byte 2 2 anl direct, #data and immediate to direct byte 3 3 orl a, rn or register to a 1 1 orl a, direct or direct byte to a 2 2 orl a, @ri or indirect ram to a 1 2 orl a, #data or immediate to a 2 2 orl direct, a or a to direct byte 2 2 orl direct, #data or immediate to direct byte 3 3 xrl a, rn exclusive-or register to a 1 1 xrl a, direct exclusive-or direct byte to a 2 2 xrl a, @ri exclusive-or indirect ram to a 1 2
c8051f020/1/2/3 104 rev. 1.4 xrl a, #data exclusive-or immediate to a 2 2 xrl direct, a exclusive-or a to direct byte 2 2 xrl direct, #data exclusive-or immedi ate to direct byte 3 3 clr a clear a 1 1 cpl a complement a 1 1 rl a rotate a left 1 1 rlc a rotate a left through carry 1 1 rr a rotate a right 1 1 rrc a rotate a right through carry 1 1 swap a swap nibbles of a 1 1 data transfer mov a, rn move register to a 1 1 mov a, direct move direct byte to a 2 2 mov a, @ri move indirect ram to a 1 2 mov a, #data move immediate to a 2 2 mov rn, a move a to register 1 1 mov rn, direct move direct byte to register 2 2 mov rn, #data move immediate to register 2 2 mov direct, a move a to direct byte 2 2 mov direct, rn move register to direct byte 2 2 mov direct, direct move direct byte to direct byte 3 3 mov direct, @ri move indirect ram to direct byte 2 2 mov direct, #data move immediate to direct byte 3 3 mov @ri, a move a to indirect ram 1 2 mov @ri, direct move direct byte to indirect ram 2 2 mov @ri, #data move immediate to indirect ram 2 2 mov dptr, #data16 load dptr with 16-bit constant 3 3 movc a, @a+dptr move code byte relative dptr to a 1 3 movc a, @a+pc move code byte relative pc to a 1 3 movx a, @ri move external data (8-bit address) to a 1 3 movx @ri, a move a to external data (8-bit address) 1 3 movx a, @dptr move external data (16-bit address) to a 1 3 movx @dptr, a move a to external data (16-bit address) 1 3 push direct push direct byte onto stack 2 2 pop direct pop direct byte from stack 2 2 xch a, rn exchange register with a 1 1 xch a, direct exchange direct byte with a 2 2 xch a, @ri exchange indirect ram with a 1 2 xchd a, @ri exchange low nibble of indirect ram with a 1 2 boolean manipulation clr c clear carry 1 1 clr bit clear direct bit 2 2 setb c set carry 1 1 setb bit set direct bit 2 2 cpl c complement carry 1 1 table 12.1. cip-51 instruction set summary mnemonic description bytes clock cycles
c8051f020/1/2/3 rev. 1.4 105 cpl bit complement direct bit 2 2 anl c, bit and direct bit to carry 2 2 anl c, /bit and complement of direct bit to carry 2 2 orl c, bit or direct bit to carry 2 2 orl c, /bit or complement of direct bit to carry 2 2 mov c, bit move direct bit to carry 2 2 mov bit, c move carry to direct bit 2 2 jc rel jump if carry is set 2 2/3 jnc rel jump if carry is not set 2 2/3 jb bit, rel jump if direct bit is set 3 3/4 jnb bit, rel jump if direct bit is not set 3 3/4 jbc bit, rel jump if direct bit is set and clear bit 3 3/4 program branching acall addr11 absolute subroutine call 2 3 lcall addr16 long subroutine call 3 4 ret return from subroutine 1 5 reti return from interrupt 1 5 ajmp addr11 absolute jump 2 3 ljmp addr16 long jump 3 4 sjmp rel short jump (relative address) 2 3 jmp @a+dptr jump indirect relative to dptr 1 3 jz rel jump if a equals zero 2 2/3 jnz rel jump if a does not equal zero 2 2/3 cjne a, direct, rel compare direct byte to a and jump if not equal 3 3/4 cjne a, #data, rel compare immediate to a and jump if not equal 3 3/4 cjne rn, #data, rel compare immediate to regist er and jump if not equal 3 3/4 cjne @ri, #data, rel compare immediate to indir ect and jump if not equal 3 4/5 djnz rn, rel decrement register an d jump if not zero 2 2/3 djnz direct, rel decrement direct byte and jump if not zero 3 3/4 nop no operation 1 1 table 12.1. cip-51 instruction set summary mnemonic description bytes clock cycles
c8051f020/1/2/3 106 rev. 1.4 notes on registers, operands and addressing modes: rn - register r0-r7 of the curr ently selected register bank. @ri - data ram location addressed indirectly through r0 or r1. rel - 8-bit, signed (two?s complement) offset relative to th e first byte of the following instruction. used by sjmp and all conditional jumps. direct - 8-bit internal data location?s address. this coul d be a direct-access data ra m location (0x00-0x7f) or an sfr (0x80-0xff). #data - 8-bit constant #data16 - 16-bit constant bit - direct-accessed bit in data ram or sfr addr11 - 11-bit destination address used by acall and ajmp . the destination must be within the same 2k-byte page of program memory as the first byte of the following instruction. addr16 - 16-bit destination address used by lcall and ljmp. the destination may be anywhere within the 64k- byte program memory space. there is one unused opcode (0xa5) that performs the same function as nop. all mnemonics copyrighted ? intel corporation 1980.
c8051f020/1/2/3 rev. 1.4 107 12.2. memory organization the memory organization of the cip-51 system controller is similar to that of a standard 8051. there are two sepa - rate memory spaces: program memory and data memory. pr ogram and data memory share the same address space but are accessed via different instru ction types. there are 256 bytes of internal data memory and 64k bytes of internal program memory address space implemen ted within the cip-51. the cip-51 memory organization is shown in figure 12.2 . 12.2.1. program memory the cip-51 has a 64k byte program memory space. the mcu implements 65536 bytes of this program memory space as in-system re-programmed flash memory, organi zed in a contiguous block from addresses 0x0000 to 0xffff. note: 512 bytes (0xee00 to 0xffff) of this memory are reserved for factory us e and are not available for user program storage. program memory is normally assumed to be read-only. ho wever, the cip-51 can write to program memory by setting the program store write enable bit (p sctl.0) and using the movx instruction. this feature provides a mechanism for the cip-51 to update program code and use the program memory space for non-volatile data storage. refer to sec - tion ?15. flash memory? on page 139 for further details. program/data memory (flash) (direct and indirect addressing) 0x00 0x7f upper 128 ram (indirect addressing only) 0x80 0xff special function register's (direct addressing only) data memory (ram) general purpose registers 0x1f 0x20 0x2f bit addressable lower 128 ram (direct and indirect addressing) 0x30 internal data address space external data address space xram - 4096 bytes (accessable using movx instruction) 0x0000 0x0fff off-chip xram space 0x1000 0xffff flash (in-system programmable in 512 byte sectors) 0x0000 0xffff reserved 0xfe00 0xfdff scrachpad memory (data only) 0x1007f 0x10000 figure 12.2. memory map
c8051f020/1/2/3 108 rev. 1.4 12.2.2. data memory the cip-51 implements 256 bytes of internal ram mapped into the data memory space from 0x00 through 0xff. the lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. either direct or indirect addressing may be used to access the lower 128 bytes of data memory. locations 0x00 through 0x1f are addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers. the next 16 bytes, locations 0x20 through 0x2f, may ei ther be addressed as bytes or as 128 bit locations accessible with the direct addressing mode. the upper 128 bytes of data memory are accessible only by indir ect addressing. this regi on occupies the same address space as the special function regi sters (sfr) but is physically separa te from the sfr space. the addressing mode used by an instruction when accessing locations above 0x7f determ ines whether the cpu accesses the upper 128 bytes of data memory space or the sfrs. instructions that use direct addressing will access the sfr space. instructions using indirect addre ssing above 0x7f access the upper 128 bytes of data memory. figure 12.2 illustrates the data memory organization of the cip-51. 12.2.3. general purpose registers the lower 32 bytes of data memory, locations 0x00 through 0x1f, may be addressed as f our banks of general-purpose registers. each bank consists of eigh t byte-wide registers designated r0 through r7. only one of these banks may be enabled at a time. two bits in the program status word, rs 0 (psw.3) and rs1 (psw.4), se lect the active register bank (see description of the psw in figure 12.6 ). this allows fast context switchin g when entering subroutines and inter - rupt service routines. indirect addressing mode s use registers r0 and r1 as index registers. 12.2.4. bit addressable locations in addition to direct access to data me mory organized as bytes, the sixteen da ta memory locations at 0x20 through 0x2f are also accessible as 128 individually addressable bits. each bit has a bit address from 0x00 to 0x7f. bit 0 of the byte at 0x20 has bit address 0x00 while bit 7 of the byte at 0x20 has bit address 0x07. bit 7 of the byte at 0x2f has bit address 0x7f. a bit access is distingui shed from a full byte access by the type of instruction used (bit source or destination operands as opposed to a byte source or destination). the mcs-51? assembly language allows an alternate notati on for bit addressing of the form xx.b where xx is the byte address and b is the bit position within the byte. for example, the instruction: mov c, 22.3h moves the boolean value at 0x13 (bit 3 of the byte at location 0x22) into the carry flag. 12.2.5. stack a programmer's stack can be lo cated anywhere in the 256 byte data memory . the stack area is designated using the stack pointer (sp, address 0x81) sfr. the sp will point to the last location used. the next value pushed on the stack is placed at sp+1 and then sp is incremented. a reset initia lizes the stack pointer to location 0x07; therefore, the first value pushed on the stack is placed at location 0x08, which is also the first register (r0) of register bank 1. thus, if more than one register bank is to be used, the sp should be initialized to a location in the data memory not being used for data storage. the stack depth can extend up to 256 bytes. the mcus also have built-in hardware for a stack record . the stack record is a 32-b it shift register, where each push or incremen t sp pushes one record bit onto the register, and each call pushes two record bits onto the regis - ter. (a pop or decrement sp pops one record bit, and a ret pops two record bits, also.) the stack record circuitry can also detect an overflow or underflow on the 32-bit shif t register, and can notify the de bug software even with the mcu running at speed.
c8051f020/1/2/3 rev. 1.4 109 12.2.6. special function registers the direct-access data memory locations from 0x80 to 0xff const itute the special function registers (sfrs). the sfrs provide control and data exchange with the cip-51's resources and peripher als. the cip-51 d uplicates the sfrs found in a typical 8051 implementation as well as impl ementing additional sfrs used to configure and access the sub-systems unique to the mcu. this allows the addition of new functionality while retaining compatibility with the mcs-51? instruction set. table 12.2 lists the sfrs implemented in the cip-51 system controller. the sfr registers are accessed anytime the direct addressing mode is used to access memory locations from 0x80 to 0xff. sfrs with addresses ending in 0x0 or 0x8 (e.g. p0 , tcon, p1, scon, ie, etc.) ar e bit-addressable as well as byte-addressable. all other sfrs are by te-addressable only. unoccupied addre sses in the sfr space are reserved for future use. accessing these areas will have an indeterminat e effect and should be avoided. refer to the corresponding pages of the datasheet, as indicated in table 12.3 , for a detailed description of each register. table 12.3. special function registers sfrs are listed in alphabetical order. al l undefined sfr locations are reserved. register address description page no. acc 0xe0 accumulator page 115 adc0cf 0xbc adc0 configuration page 49 *, page 65 ** adc0cn 0xe8 adc0 control page 50 *, page 66 ** adc0gth 0xc5 adc0 greater-than high page 53 *, page 69 ** adc0gtl 0xc4 adc0 greater-than low page 53 *, page 69 ** adc0h 0xbf adc0 data word high page 51 *, page 67 ** adc0l 0xbe adc0 data word low page 51 *, page 67 ** table 12.2. special function re gister (sfr) memory map f8 spi0cn pca0h pca0cph0 pca0cph1 pc a0cph2 pca0cph3 pca0cph4 wdtcn f0 b scon1 sbuf1 saddr1 tl4 th4 eip1 eip2 e8 adc0cn pca0l pca0cpl0 pca0cpl1 pca 0cpl2 pca0cpl3 pca0cpl4 rstsrc e0 acc xbr0 xbr1 xbr2 rcap4l rcap4h eie1 eie2 d8 pca0cn pca0md pca0cpm0 pca0cpm1 pca0cpm2 pca0cpm3 pca0cpm4 d0 psw ref0cn dac0l dac0h dac0cn dac1l dac1h dac1cn c8 t2con t4con rcap2l rcap2h tl2 th2 smb0cr c0 smb0cn smb0sta smb0dat smb0adr adc0gtl adc0gth adc0ltl adc0lth b8 ip saden0 amx0cf amx0sl adc0cf p1mdin adc0l adc0h b0 p3 oscxcn oscicn p74out? flscl flacl a8 ie saddr0 adc1cn adc1cf amx1sl p3if saden1 emi0cn a0 p2 emi0tc emi0cf p0mdout p1mdout p2mdout p3mdout 98 scon0 sbuf0 spi0cfg spi0dat adc1 spi0ckr cpt0cn cpt1cn 90 p1 tmr3cn tmr3rll tmr3rlh tmr3l tmr3h p7? 88 tcon tmod tl0 tl1 th0 th1 ckcon psctl 80 p0 sp dpl dph p4? p5? p6? pcon 0(8) 1(9) 2(a) 3(b) 4(c) 5(d) 6(e) 7(f) (bit addressable)
c8051f020/1/2/3 110 rev. 1.4 adc0lth 0xc7 adc0 less-than high page 53 *, page 69 ** adc0ltl 0xc6 adc0 less-than low page 53 *, page 69 ** adc1cf 0xab adc1 analog multiplexer configuration page 79 adc1cn 0xaa adc1 control page 80 adc1 0x9c adc1 data word page 81 amx0cf 0xba adc0 multiplexer configuration page 47 *, page 63 ** amx0sl 0xbb adc0 multiplexer channel select page 48 *, page 64 ** amx1sl 0xac adc1 analog multiplexer channel select page 79 b 0xf0 b register page 115 ckcon 0x8e clock control page 226 cpt0cn 0x9e comparator 0 control page 97 cpt1cn 0x9f comparator 1 control page 98 dac0cn 0xd4 dac0 control page 86 dac0h 0xd3 dac0 high page 85 dac0l 0xd2 dac0 low page 85 dac1cn 0xd7 dac1 control page 88 dac1h 0xd6 dac1 high byte page 87 dac1l 0xd5 dac1 low byte page 87 dph 0x83 data pointer high page 113 dpl 0x82 data pointer low page 113 eie1 0xe6 extended interrupt enable 1 page 121 eie2 0xe7 extended interrupt enable 2 page 122 eip1 0xf6 external interrupt priority 1 page 123 eip2 0xf7 external interrupt priority 2 page 124 emi0cn 0xaf external memory interface control page 147 emi0cf 0xa3 emif configuration page 147 emi0tc 0xa1 emif timing control page 152 flacl 0xb7 flash access limit page 142 flscl 0xb6 flash scale page 143 ie 0xa8 interrupt enable page 119 ip 0xb8 interrupt priority page 120 oscicn 0xb2 internal oscillator control page 136 oscxcn 0xb1 external oscillator control page 137 p0 0x80 port 0 latch page 173 p0mdout 0xa4 port 0 output mode configuration page 173 p1 0x90 port 1 latch page 174 p1mdin 0xbd port 1 input mode page 174 p1mdout 0xa5 port 1 output mode configuration page 175 p2 0xa0 port 2 latch page 175 p2mdout 0xa6 port 2 output mode configuration page 175 p3 0xb0 port 3 latch page 176 p3if 0xad port 3 interrupt flags page 177 p3mdout 0xa7 port 3 output mode configuration page 176 ?p4 0x84 port 4 latch page 180 ? ?p5 0x85 port 5 latch page 180 ? table 12.3. special function registers sfrs are listed in alphabetical order. al l undefined sfr locations are reserved. register address description page no.
c8051f020/1/2/3 rev. 1.4 111 ?p6 0x86 port 6 latch page 181 ? ?p7 0x96 port 7 latch page 181 ? ?p74out 0xb5 port 4 through 7 output mode page 179 ? pca0cn 0xd8 pca control page 259 pca0cph0 0xfa pca capture 0 high page 263 pca0cph1 0xfb pca capture 1 high page 263 pca0cph2 0xfc pca capture 2 high page 263 pca0cph3 0xfd pca capture 3 high page 263 pca0cph4 0xfe pca capture 4 high page 263 pca0cpl0 0xea pca capture 0 low page 263 pca0cpl1 0xeb pca capture 1 low page 263 pca0cpl2 0xec pca capture 2 low page 263 pca0cpl3 0xed pca capture 3 low page 263 pca0cpl4 0xee pca capture 4 low page 263 pca0cpm0 0xda pca module 0 mode register page 261 pca0cpm1 0xdb pca module 1 mode register page 261 pca0cpm2 0xdc pca module 2 mode register page 261 pca0cpm3 0xdd pca module 3 mode register page 261 pca0cpm4 0xde pca module 4 mode register page 261 pca0h 0xf9 pca counter high page 262 pca0l 0xe9 pca counter low page 262 pca0md 0xd9 pca mode page 260 pcon 0x87 power control page 126 psctl 0x8f program store r/w control page 144 psw 0xd0 program status word page 114 rcap2h 0xcb timer/counter 2 capture high page 239 rcap2l 0xca timer/counter 2 capture low page 239 rcap4h 0xe5 timer/counter 4 capture high page 248 rcap4l 0xe4 timer/counter 4 capture low page 248 ref0cn 0xd1 programmable voltage reference control page 92 ?, page 94 ?? rstsrc 0xef reset source register page 132 saddr0 0xa9 uart0 slave address page 214 saddr1 0xf3 uart1 slave address page 224 saden0 0xb9 uart0 slave address enable page 214 saden1 0xae uart1 slave address enable page 224 sbuf0 0x99 uart0 data buffer page 214 sbuf1 0xf2 uart1 data buffer page 224 scon0 0x98 uart0 control page 213 scon1 0xf1 uart1 control page 223 smb0adr 0xc3 smbus slave address page 193 smb0cn 0xc0 smbus control page 191 smb0cr 0xcf smbus clock rate page 192 smb0dat 0xc2 smbus data page 193 smb0sta 0xc1 smbus status page 194 sp 0x81 stack pointer page 113 table 12.3. special function registers sfrs are listed in alphabetical order. al l undefined sfr locations are reserved. register address description page no.
c8051f020/1/2/3 112 rev. 1.4 spi0cfg 0x9a spi configuration page 201 spi0ckr 0x9d spi clock rate control page 203 spi0cn 0xf8 spi control page 202 spi0dat 0x9b spi data page 203 t2con 0xc8 timer/counter 2 control page 238 t4con 0xc9 timer/counter 4 control page 247 tcon 0x88 timer/counter control page 231 th0 0x8c timer/counter 0 high page 233 th1 0x8d timer/counter 1 high page 233 th2 0xcd timer/counter 2 high page 239 th4 0xf5 timer/counter 4 high page 248 tl0 0x8a timer/counter 0 low page 233 tl1 0x8b timer/counter 1 low page 233 tl2 0xcc timer/counter 2 low page 239 tl4 0xf4 timer/counter 4 low page 248 tmod 0x89 timer/counter mode page 232 tmr3cn 0x91 timer 3 control page 241 tmr3h 0x95 timer 3 high page 242 tmr3l 0x94 timer 3 low page 242 tmr3rlh 0x93 timer 3 reload high page 242 tmr3rll 0x92 timer 3 reload low page 241 wdtcn 0xff watchdog timer control page 131 xbr0 0xe1 port i/o crossbar control 0 page 170 xbr1 0xe2 port i/o crossbar control 1 page 171 xbr2 0xe3 port i/o crossbar control 2 page 172 0x97, 0xa2, 0xb3, 0xb4, 0xce, 0xdf reserved * refers to a register in the c8051f020/1 only. ** refers to a register in the c8051f022/3 only. ? refers to a register in the c8051f020/2 only. ?? refers to a register in the c8051f021/3 only. table 12.3. special function registers sfrs are listed in alphabetical order. al l undefined sfr locations are reserved. register address description page no.
c8051f020/1/2/3 rev. 1.4 113 12.2.7. register descriptions following are descriptions of sfrs related to the operation of the cip-51 system controller. reserved bits should not be set to logic l. future product versions may use these bits to im plement new features in which case the reset value of the bit will be logic 0, selecting the feature's default state. detailed descriptions of the remaining sfrs are included in the sections of the datasheet associated with their corresponding system function. figure 12.3. sp: stack pointer bits7-0: sp: stack pointer. the stack pointer holds the location of the top of the stack. the stack pointer is incremented before every push operation. the sp register defaults to 0x07 after reset. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x81 figure 12.4. dpl: data pointer low byte bits7-0: dpl: data pointer low. the dpl register is the low byte of the 16-bit dptr. dptr is us ed to access indirectly addressed xram and flash memory. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x82 figure 12.5. dph: data pointer high byte bits7-0: dph: data pointer high. the dph register is the high byte of the 16-bit dptr. dptr is used to access indirectly addressed xram and flash memory. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x83
c8051f020/1/2/3 114 rev. 1.4 figure 12.6. psw: program status word bit7: cy: carry flag. this bit is set when the last arithmetic operation resulted in a carry (addit ion) or a borrow (subtrac- tion). it is cleared to 0 by a ll other arithmetic operations. bit6: ac: auxili ary carry flag this bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow from (subtraction) the high order nibble. it is cleared to 0 by all other arithmetic operations. bit5: f0: user flag 0. this is a bit-addressable, general purpos e flag for use under software control. bits4-3: rs1-rs0: register bank select. these bits select which register ba nk is used during register accesses. bit2: ov: overflow flag. this bit is set to 1 if the last arithmetic operation resulted in a carry (additi on), borrow (subtraction), or overflow (multiply or divide). it is cl eared to 0 by all other arithmetic operations. bit1: f1: user flag 1. this is a bit-addressable, general purpos e flag for use under software control. bit0: parity: parity flag. this bit is set to 1 if the sum of the eight bits in the accumulator is odd and cl eared if the sum is even. r/w r/w r/w r/w r/w r/w r/w r reset value cy ac f0 rs1 rs0 ov f1 parity 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xd0 rs1 rs0 register bank address 0 0 0 0x00 - 0x07 0 1 1 0x08 - 0x0f 1 0 2 0x10 - 0x17 1 1 3 0x18 - 0x1f
c8051f020/1/2/3 rev. 1.4 115 figure 12.7. acc: accumulator bits7-0: acc: accumulator. this register is the accumula tor for arithme tic operations. r/w r/w r/w r/w r/w r/w r/w r/w reset value acc.7 acc.6 acc.5 acc.4 acc .3 acc.2 acc.1 acc.0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xe0 figure 12.8. b: b register bits7-0: b: b register. this register serves as a second accumula tor for certain arithmetic operations. r/w r/w r/w r/w r/w r/w r/w r/w reset value b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xf0
c8051f020/1/2/3 116 rev. 1.4 12.3. interrupt handler the cip-51 includes an extended interrupt system supporting a total of 22 interrupt sources with two priority levels. the allocation of interrupt so urces between on-chip peripherals and extern al inputs pins varies according to the spe - cific version of the device. each interr upt source has one or more associated in terrupt-pending flag(s) located in an sfr. when a peripheral or external s ource meets a valid interrupt condition, the associated interrupt-pending flag is set to logic 1. if interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is set. as soon as execution of the current instruction is complete, th e cpu generates an lcall to a predetermined address to begin execution of an interrupt service routine (isr). each isr must end with an reti instruction, which returns pro - gram execution to the next instruction that would have b een executed if the interrupt request had not occurred. if interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution continues as normal. (the interrupt-pending flag is set to logic 1 regardless of the interrup t's enable/disable state.) each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in an sfr (ie-eie2). however, interrupts must first be gl obally enabled by setting the ea bit (ie.7) to logic 1 before the individual interrupt enables are recognized. setting the ea bit to logic 0 disables all inte rrupt sources regardless of the individual interrupt-enable settings. some interrupt-pending flags are automa tically cleared by the hardware when the cpu vectors to the isr. however, most are not cleared by the ha rdware and must be cleared by software befo re returning from the isr. if an interrupt- pending flag remains set after the cpu completes the retu rn-from-interrupt (reti) in struction, a new interrupt request will be generated immediately and the cpu will re-ent er the isr after the completi on of the next instruction. 12.3.1. mcu interrupt sources and vectors the mcus support 22 interrupt sources. software can simu late an interrupt event by setting any interrupt-pending flag to logic 1. if interrupts are enabled for the flag, an interrupt request will be generated and the cpu will vector to the isr address associated with the inte rrupt-pending flag. mcu interrupt sources , associated vector addresses, prior - ity order and control bi ts are summarized in table 12.4 . refer to the datasheet section as sociated with a particular on- chip peripheral for information regarding valid interrupt c onditions for the peripheral and the behavior of its inter - rupt-pending flag(s). 12.3.2. external interrupts two of the external interrupt sources (/int0 and /int1) ar e configurable as active-low level-sensitive or active-low edge-sensitive inputs depending on the setting of bits it0 (tcon.0) and it1 (tc on.2). ie0 (tcon.1) and ie1 (tcon.3) serve as the interrupt-pending fl ag for the /int0 and /int1 external interrup ts, respectively. if an /int0 or /int1 external interrupt is configured as edge-sensitive, the corresponding in terrupt-pending flag is automatically cleared by the hardware when the cpu v ectors to the isr. when configured as level sensitive, the interrupt-pending flag follows the state of the external in terrupt's input pin. the external interrupt source must hold the input active until the interrupt request is recognized. it mu st then deactivate the interrupt request before execution of the isr completes or another interrupt request will be generated. the remaining 2 external interrupts (external interrupts 6- 7) are edge-sensitive inputs c onfigurable as active-low or active-high. the interrupt-pending flags and configuration bits for these interrupts are in the port 3 interrupt flag register shown in figure ?17.19 p3if: port3 interrupt fl ag register? on page 177 .
c8051f020/1/2/3 rev. 1.4 117 table 12.4. interrupt summary interrupt source interrupt vector priority order pending flag bit addressable? cleared by hw? enable flag priority control reset 0x0000 top none n/a n/a always enabled always highest external interrupt 0 (/int0) 0x0003 0 ie0 (tcon.1) y y ex0 (ie.0) px0 (ip.0) timer 0 overflow 0x000b 1 tf0 (tcon.5) y y et0 (ie.1) pt0 (ip.1) external interrupt 1 (/int1) 0x0013 2 ie1 (tcon.3) y y ex1 (ie.2) px1 (ip.2) timer 1 overflow 0x001b 3 tf1 (tcon.7) y y et1 (ie.3) pt1 (ip.3) uart0 0x0023 4 ri0 (scon0.0) ti0 (scon0.1) y es0 (ie.4) ps0 (ip.4) timer 2 overflow (or exf2) 0x002b 5 tf2 (t2con.7) y et2 (ie.5) pt2 (ip.5) serial peripheral interface 0x0033 6 spif (spi0cn.7) y espi0 (eie1.0) pspi0 (eip1.0) smbus interface 0x003b 7 si (smb0cn.3) y esmb0 (eie1.1) psmb0 (eip1.1) adc0 window comparator 0x0043 8 ad0wint (adc0cn.2) y ewadc0 (eie1.2) pwadc0 (eip1.2) programmable counter array 0x004b 9 cf (pca0cn.7) ccfn (pca0cn.n) y epca0 (eie1.3) ppca0 (eip1.3) comparator 0 falling edge 0x0053 10 cp0fif (cpt0cn.4) ecp0f (eie1.4) pcp0f (eip1.4) comparator 0 rising edge 0x005b 11 cp0rif (cpt0cn.5) ecp0r (eie1.5) pcp0r (eip1.5) comparator 1 falling edge 0x0063 12 cp1fif (cpt1cn.4) ecp1f (eie1.6) pcp1f (eip1.6) comparator 1 rising edge 0x006b 13 cp1rif (cpt1cn.5) ecp1r (eie1.7) pcp1f (eip1.7) timer 3 overflow 0x0073 14 tf3 (tmr3cn.7) et3 (eie2.0) pt3 (eip2.0) adc0 end of conversion 0x007b 15 ad0int (adc0cn.5) y eadc0 (eie2.1) padc0 (eip2.1) timer 4 overflow 0x0083 16 tf4 (t4con.7) et4 (eie2.2) pt4 (eip2.2) adc1 end of conversion 0x008b 17 ad1int (adc1cn.5) eadc1 (eie2.3) padc1 (eip2.3) external interrupt 6 0x0093 18 ie6 (p3if.5) ex6 (eie2.4) px6 (eip2.4) external interrupt 7 0x009b 19 ie7 (p3if.6) ex7 (eie2.5) px7 (eip2.5) uart1 0x00a3 20 ri1 (scon1.0) ti1 (scon1.1) es1 ps1 external crystal osc ready 0x00ab 21 xtlvld (oscxcn.7) exvld (eie2.7) pxvld (eip2.7)
c8051f020/1/2/3 118 rev. 1.4 12.3.3. interrupt priorities each interrupt source can be individually programmed to one of two priority leve ls: low or high. a low priority inter - rupt service routine can be preempted by a high priority inte rrupt. a high priority interrupt cannot be preempted. each interrupt has an associated interrupt priority bit in an sfr (ip-eip2) used to configure its priority level. low priority is the default. if two interrupts are recognized simultaneously, th e interrupt with the higher priority is serviced first. if both interrupts have the same priority level, a fixe d priority order is used to arbitrate, given in table 12.4 . 12.3.4. interrupt latency interrupt response time depends on the state of the cpu wh en the interrupt occurs. pending interrupts are sampled and priority decoded each system clock cycle. ther efore, the fastest possib le response time is 5 system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the lcall to the isr. if an interrupt is pending when a reti is executed, a single instru ction is executed before an lcall is made to service the pending interrupt. therefore, the maximum response time for an interrupt (whe n no other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the cpu is performing an reti instruction followed by a div as the next instruction. in this case, the response time is 18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the reti, 8 clock cycles to complete the div instruction and 4 clock cycles to execute the lcall to the isr. if the cpu is executing an is r for an interrupt with equal or higher priority, the new interrupt will not be serviced until the current is r completes, including the reti and following instruction.
c8051f020/1/2/3 rev. 1.4 119 12.3.5. interrupt register descriptions the sfrs used to enable the interrupt sources and set their priority level are described below. refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). figure 12.9. ie: interrupt enable bit7: ea: enable all interrupts. this bit globally enables/disables all interrupts. when set to ?0?, individual interrupt mask settings are overridden. 0: disable all interrupt sources. 1: enable each interr upt according to its i ndividual mask setting. bit6: iegf0: general purpose flag 0. this is a general purpose flag for use under software control. bit5: et2: enabler timer 2 interrupt. this bit sets the masking of the timer 2 interrupt. 0: disable timer 2 interrupt. 1: enable interrupt requests generated by the tf2 flag (t2con.7). bit4: es0: enable uart0 interrupt. this bit sets the masking of the uart0 interrupt. 0: disable uart0 interrupt. 1: enable uart0 interrupt. bit3: et1: enable timer 1 interrupt. this bit sets the masking of the timer 1 interrupt. 0: disable all timer 1 interrupt. 1: enable interrupt requests generated by the tf1 flag (tcon.7). bit2: ex1: enable external interrupt 1. this bit sets the masking of external interrupt 1. 0: disable external interrupt 1. 1: enable interrupt requests generated by the /int1 pin. bit1: et0: enable timer 0 interrupt. this bit sets the masking of the timer 0 interrupt. 0: disable all timer 0 interrupt. 1: enable interrupt requests generated by the tf0 flag (tcon.5). bit0: ex0: enable external interrupt 0. this bit sets the masking of external interrupt 0. 0: disable external interrupt 0. 1: enable interrupt requests generated by the /int0 pin. r/w r/w r/w r/w r/w r/w r/w r/w reset value ea iegf0 et2 es0 et1 ex1 et0 ex0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xa8
c8051f020/1/2/3 120 rev. 1.4 figure 12.10. ip: interrupt priority bits7-6: unused. read = 11b, write = don't care. bit5: pt2: timer 2 interrupt priority control. this bit sets the priority of the timer 2 interrupt. 0: timer 2 interrupt priority determined by default priority order. 1: timer 2 interrupts set to high priority level. bit4: ps0: uart0 interrupt priority control. this bit sets the priority of the uart0 interrupt. 0: uart0 interrupt priority determ ined by default priority order. 1: uart0 interrupts set to high priority level. bit3: pt1: timer 1 interrupt priority control. this bit sets the priority of the timer 1 interrupt. 0: timer 1 interrupt priority determined by default priority order. 1: timer 1 interrupts set to high priority level. bit2: px1: external interrupt 1 priority control. this bit sets the priority of the ex ternal interrupt 1 interrupt. 0: external interrupt 1 priority determined by default priority order. 1: external interrupt 1 set to high priority level. bit1: pt0: timer 0 interrupt priority control. this bit sets the priority of the timer 0 interrupt. 0: timer 0 interrupt priority determined by default priority order. 1: timer 0 interrupt set to high priority level. bit0: px0: external interrupt 0 priority control. this bit sets the priority of the ex ternal interrupt 0 interrupt. 0: external interrupt 0 priority determined by default priority order. 1: external interrupt 0 set to high priority level. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - pt2 ps0 pt1 px1 pt0 px0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xb8
c8051f020/1/2/3 rev. 1.4 121 figure 12.11. eie1: extended interrupt enable 1 bit7: ecp1r: enable comparator 1 (cp1) rising edge interrupt. this bit sets the masking of the cp1 interrupt. 0: disable cp1 rising edge interrupt. 1: enable interrupt requests generated by the cp1rif flag (cpt1cn.5). bit6: ecp1f: enable comparator (cp1) falling edge interrupt. this bit sets the masking of the cp1 interrupt. 0: disable cp1 falling edge interrupt. 1: enable interrupt requests generated by the cp1fif flag (cpt1cn.4). bit5: ecp0r: enable comparator 0 (cp0) rising edge interrupt. this bit sets the masking of the cp0 interrupt. 0: disable cp0 rising edge interrupt. 1: enable interrupt requests generated by the cp0rif flag (cpt0cn.5). bit4: ecp0f: enable comparator0 (cp0) falling edge interrupt. this bit sets the masking of the cp0 interrupt. 0: disable cp0 falling edge interrupt. 1: enable interrupt requests generated by the cp0fif flag (cpt0cn.4). bit3: epca0: enable programmable counter array (pca0) interrupt. this bit sets the masking of the pca0 interrupts. 0: disable all pca0 interrupts. 1: enable interrupt requests generated by pca0. bit2: ewadc0: enable window comparison adc0 interrupt. this bit sets the masking of adc0 window comparison interrupt. 0: disable adc0 window comparison interrupt. 1: enable interrupt requests generated by adc0 window comparisons. bit1: esmb0: enable system management bus (smbus0) interrupt. this bit sets the masking of the smbus interrupt. 0: disable all smbus interrupts. 1: enable interrupt requests generated by the si flag (smb0cn.3). bit0: espi0: enable serial periph eral interface (spi 0) interrupt. this bit sets the masking of spi0 interrupt. 0: disable all spi0 interrupts. 1: enable interrupt requests generated by the spif flag (spi0cn.7). r/w r/w r/w r/w r/w r/w r/w r/w reset value ecp1r ecp1f ecp0r ecp0f epca0 ewadc0 esmb0 espi0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe6
c8051f020/1/2/3 122 rev. 1.4 figure 12.12. eie2: extended interrupt enable 2 bit7: exvld: enable external clock source valid (xtlvld) interrupt. this bit sets the masking of the xtlvld interrupt. 0: disable xtlvld interrupt. 1: enable interrupt requests generated by the xtlvld flag (oscxcn.7) bit6: es1: enable uart1 interrupt. this bit sets the masking of the uart1 interrupt. 0: disable uart1 interrupt. 1: enable uart1 interrupt. bit5: ex7: enable external interrupt 7. this bit sets the masking of external interrupt 7. 0: disable external interrupt 7. 1: enable interrupt requests generated by the external interrupt 7 input pin. bit4: ex6: enable external interrupt 6. this bit sets the masking of external interrupt 6. 0: disable external interrupt 6. 1: enable interrupt requests generated by the external interrupt 6 input pin. bit3: eadc1: enable adc1 end of conversion interrupt. this bit sets the masking of the adc1 end of conversion interrupt. 0: disable adc1 end of conversion interrupt. 1: enable interrupt requests generated by the adc1 end of conversion interrupt. bit2: et4: enable timer 4 interrupt this bit sets the masking of the timer 4 interrupt. 0: disable timer 4 interrupt. 1: enable interrupt requests generated by the tf4 flag (t4con.7). bit1: eadc0: enable adc0 end of conversion interrupt. this bit sets the masking of the adc0 end of conversion interrupt. 0: disable adc0 conversion interrupt. 1: enable interrupt requests generated by the adc0 conversion interrupt. bit0: et3: enable timer 3 interrupt. this bit sets the masking of the timer 3 interrupt. 0: disable all timer 3 interrupts. 1: enable interrupt requests generated by the tf3 flag (tmr3cn.7). r/w r/w r/w r/w r/w r/w r/w r/w reset value exvld es1 ex7 ex6 eadc1 et4 eadc0 et3 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe7
c8051f020/1/2/3 rev. 1.4 123 figure 12.13. eip1: extended interrupt priority 1 bit7: pcp1r: comparator1 (cp1) rising interrupt priority control. this bit sets the priority of the cp1 interrupt. 0: cp1 rising interrupt set to low priority level. 1: cp1 rising interrupt set to high priority level. bit6: pcp1f: comparator1 (cp1) fall ing interrupt priority control. this bit sets the priority of the cp1 interrupt. 0: cp1 falling interrupt set to low priority level. 1: cp1 falling interrupt set to high priority level. bit5: pcp0r: comparator0 (cp0) rising interrupt priority control. this bit sets the priority of the cp0 interrupt. 0: cp0 rising interrupt set to low priority level. 1: cp0 rising interrupt set to high priority level. bit4: pcp0f: comparator0 (cp0) fall ing interrupt priority control. this bit sets the priority of the cp0 interrupt. 0: cp0 falling interrupt set to low priority level. 1: cp0 falling interrupt set to high priority level. bit3: ppca0: programmable counter array (pca0) interrupt priority control. this bit sets the priority of the pca0 interrupt. 0: pca0 interrupt set to low priority level. 1: pca0 interrupt set to high priority level. bit2: pwadc0: adc0 window comparator interrupt priority control. this bit sets the priority of the adc0 window interrupt. 0: adc0 window interrupt set to low priority level. 1: adc0 window interrupt set to high priority level. bit1: psmb0: system management bus (smbus0) interrupt priority control. this bit sets the priority of the smbus0 interrupt. 0: smbus interrupt set to low priority level. 1: smbus interrupt set to high priority level. bit0: pspi0: serial periph eral interface (spi0) inte rrupt prior ity control. this bit sets the priority of the spi0 interrupt. 0: spi0 interrupt set to low priority level. 1: spi0 interrupt set to high priority level. r/w r/w r/w r/w r/w r/w r/w r/w reset value pcp1r pcp1f pcp0r pcp0f ppca0 pwadc0 psmb0 pspi0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf6
c8051f020/1/2/3 124 rev. 1.4 figure 12.14. eip2: extended interrupt priority 2 bit7: pxvld: external clock source valid (xtlvld) interrupt priority control. this bit sets the priority of the xtlvld interrupt. 0: xtlvld interrupt set to low priority level. 1: xtlvld interrupt set to high priority level. bit6: ep1: uart1 interrupt priority control. this bit sets the priority of the uart1 interrupt. 0: uart1 interrupt set to low priority. 1: uart1 interrupt set to high priority. bit5: px7: external interrupt 7 priority control. this bit sets the priority of the external interrupt 7. 0: external interrupt 7 set to low priority level. 1: external interrupt 7 set to high priority level. bit4: px6: external interrupt 6 priority control. this bit sets the priority of the external interrupt 6. 0: external interrupt 6 set to low priority level. 1: external interrupt 6 set to high priority level. bit3: padc1: adc1 end of conversi on interrupt priority control. this bit sets the priority of the adc1 end of conversion interrupt. 0: adc1 end of conversion interrupt set to low priority. 1: adc1 end of conversion interrupt set to low priority. bit2: pt4: timer 4 interrupt priority control. this bit sets the priority of the timer 4 interrupt. 0: timer 4 interrupt set to low priority. 1: timer 4 interrupt set to low priority. bit1: padc0: adc end of conversion interrupt priority control. this bit sets the priority of the adc0 end of conversion interrupt. 0: adc0 end of conversion interrupt set to low priority level. 1: adc0 end of conversion interrupt set to high priority level. bit0: pt3: timer 3 interrupt priority control. this bit sets the priority of the timer 3 interrupts. 0: timer 3 interrupt priority determined by default priority order. 1: timer 3 interrupt set to high priority level. r/w r/w r/w r/w r/w r/w r/w r/w reset value pxvld ep1 px7 px6 padc1 pt4 padc0 pt3 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf7
c8051f020/1/2/3 rev. 1.4 125 12.4. power management modes the cip-51 core has two software programmable power mana gement modes: idle and stop. idle mode halts the cpu while leaving the external peripherals an d internal clocks active. in stop mode, the cpu is halted, all interrupts and timers (except the missing clock detector) are inactive, and the system clock is stopped. since clocks are running in idle mode, power consumption is dependent upon the system clock frequency and the number of peripherals left in active mode before entering idle. stop mode consumes the least power. figure 12.15 describes the power control register (pcon) used to control the cip-51's power management modes. although the cip-51 has idle and stop modes built in (as with any standard 8051 architecture), power management of the entire mcu is better accomplished by enabling/disabl ing individual peripherals as needed. each analog periph - eral can be disabled when not in use a nd put into low power mode. digital peripherals, such as timers or serial buses, draw little power whenever they are not in use. turning off the flash memory saves power, similar to entering idle mode. turning off the oscillator saves even more power, but requires a reset to restart the mcu. 12.4.1. idle mode setting the idle mode select bit (pcon. 0) causes the cip-51 to halt the cpu and enter idle mode as soon as the instruction that sets the bit completes. all internal regi sters and memory maintain their original data. all analog and digital peripherals can rema in active during idle mode. idle mode is terminated when an enabled interrupt or /rst is asserted. the assertion of an enabled interrupt will cause the idle mode selection bit (pc on.0) to be cleared and the cpu to re sume operation. the pending interrupt will be serviced and the next instruction to be executed after the return from interrupt (reti) will be the instruction immediately following the one that set the id le mode select bit. if idle mode is terminated by an internal or external reset, the cip-51 performs a normal reset sequen ce and begins program execu tion at address 0x0000. if enabled, the wdt will even tually cause an internal watchdog reset a nd thereby terminate the idle mode. this fea - ture protects the system from an unin tended permanent shutdown in the event of an inadvertent write to the pcon register. if this behavior is not desired, the wdt may be di sabled by software prior to entering the idle mode if the wdt was initially configured to allow this operation. th is provides the opportunity for additional power savings, allowing the system to remain in the idle mode indefinitely, waiting for an external stimulus to wake up the system. refer to section ?13.8. watchdog timer reset? on page 129 for more information on th e use and configuration of the wdt. 12.4.2. stop mode setting the stop mode select bit (pcon.1) causes the cip-51 to enter stop mode as soon as the inst ruction that sets the bit completes. in stop mode, the cpu and internal os cillator are stopped, effectively shutting down all digital peripherals. each analog peripheral must be shut down individually prior to entering stop mode. stop mode can only be terminated by an internal or external reset. on re set, the cip-51 performs the nor mal reset sequence and begins program execution at address 0x0000. if enabled, the missing clock detector will cause an internal reset and th ereby terminate the st op mode. the missing clock detector should be disabled if the cpu is to be put to sleep for longer than the mcd timeout of 100 s.
c8051f020/1/2/3 126 rev. 1.4 figure 12.15. pcon: power control bit7: smod0: uart0 baud rate doubler enable. this bit enables/disables the divide-by-two function of the uart0 baud rate logic for configurations described in the uart0 section. 0: uart0 baud rate divide-by-two enabled. 1: uart0 baud rate divide-by-two disabled. bit6: sstat0: uart0 enhanced status mode select. this bit controls the access mode of th e sm20-sm00 bits in register scon0. 0: reads/writes of sm20-sm00 access the sm20-sm00 uart0 mode setting. 1: reads/writes of sm20-sm00 access the framing error (fe0), rx overrun (rxov0), and tx collision (txcol0) status bits. bit5: reserved. read is undefined. must write 0. bit4: smod1: uart1 baud rate doubler enable. this bit enables/disables the divide-by-two function of the uart1 baud rate logic for configurations described in the uart1 section. 0: uart1 baud rate divide-by-two enabled. 1: uart1 baud rate divide-by-two disabled. bit3: sstat1: uart1 enhanced status mode select. this bit controls the access mode of the sm21-sm01 bits in scon1. 0: reads/writes of sm21-sm01 access the sm21-sm01 uart1 mode setting. 1: reads/writes of sm21-sm01 access the framing error (fe1), rx overrun (rxov1), and tx collision (txcol1) status bits. bit2: reserved. read is undefined. must write 0. bit1: stop: stop mode select. writing a ?1? to this bit will place the cip-51 into stop mode. this bit will always read ?0?. 1: cip-51 forced into power-down mode . (turns off internal oscillator). bit0: idle: idle mode select. writing a ?1? to this bit will place the cip-51 in to idle mode. this bit will always read ?0?. 1: cip-51 forced into idle mode. (shuts off clock to cpu, but clock to timers, interrupts, and all peripherals remain active.) r/w r/w r/w r/w r/w r/w r/w r/w reset value smod0 sstat0 reserved smod1 sstat1 reserved stop idle 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x87
c8051f020/1/2/3 rev. 1.4 127 13. reset sources reset circuitry allows the controller to be easily placed in a predefined default co ndition. on entry to this reset state, the following occur: ? cip-51 halts program execution ? special function registers (sfrs) are initialized to their defined reset values ? external port pins are forced to a known state ? interrupts and timers are disabled. all sfrs are reset to the predefined valu es noted in the sfr detailed descriptions. the contents of internal data mem - ory are unaffected during a reset; any pr eviously stored data is preserved. ho wever, since the stack pointer sfr is reset, the stack is effectively lost even though the data on the stack are not altered. the i/o port latches are reset to 0xff (all logic 1?s), activa ting internal weak pull-ups which take the external i/o pins to a high state. note that weak pull-up s are disabled during the reset, and enable d when the device exits the reset state. this allows power to be conserved while the part is held in reset. for vdd monitor resets, the /rst pin is driven low until the end of the vdd reset timeout. on exit from the reset state, the program counter (pc) is rese t, and the system clock defaults to the internal oscillator running at 2 mhz. refer to section ? 14. oscillators ? on page 135 for information on selecting and configuring the system clock source. the watchdog timer is enabled using its longest timeout interval (see section ? 13.8. watchdog timer reset ? on page 129 ). once the system clock source is stable, program execution begins at location 0x0000. there are seven sources for putting the mc u into the reset state: power-on/power-fail, external /rst pin, external cnvstr signal, software command, co mparator0, missing clock detector, and watchdog timer. each reset source is described in the following sections. wdt xtal1 xtal2 osc internal clock generator system clock cip-51 microcontroller core missing clock detector (one- shot) wdt strobe software reset extended interrupt handler clock select /rst + - vdd supply reset timeout (wired-or) system reset supply monitor reset funnel + - cp0+ comparator0 cp0- (port i/o) crossbar cnvstr (cnvstr reset enable) (cp0 reset enable) en wdt enable en mcd enable pre figure 13.1. reset sources
c8051f020/1/2/3 128 rev. 1.4 13.1. power-on reset the c8051f020/1/2/3 family incorporates a power supply monitor that holds the mcu in the reset state until vdd rises above the v rst level during power-up. see figure 13.2 for timing diagram, and refer to table 13.1 for the elec - trical characteristics of the power supply monitor circuit. the /rst pin is asserted low until the end of the 100 ms vdd monitor timeout in order to allow the vdd supply to stabilize. on exit from a power-on reset, the porsf flag (rstsrc.1) is set by hardware to logic 1. all of the other reset flags in the rstsrc register are indeterminat e. porsf is cleared by all other resets . since all resets cause program exe - cution to begin at the same location (0x0000), software can read the porsf flag to de termine if a power-up was the cause of reset. the contents of inte rnal data memory should be assumed to be undefined after a power-on reset. the vdd monitor function is enable d by tying the monen pin directly to vdd. this is the recommended configuration for the monen pin. . 13.2. power-fail reset when a power-down transition or power irregularity causes vdd to drop below v rst , the power supply monitor will drive the /rst pin low and return the cip-51 to the reset state. when vdd returns to a level above vrst, the cip-51 will leave the reset state in the same ma nner as that for the power-on reset (see figure 13.2 ). note that even though internal data memory contents are not altered by the powe r-fail reset, it is impossible to determine if vdd dropped below the level required for data retention. if the porsf flag is set to logic 1, the data may no longer be valid. vdd monitor reset power-on reset /rst t volts 1.0 2.0 logic high logic low 100ms 100ms v d d 2.70 2.55 v rst figure 13.2. reset timing
c8051f020/1/2/3 rev. 1.4 129 13.3. external reset the external /rst pin provides a means for external circuitr y to force the mcu into a reset state. asserting the /rst pin low will cause the mcu to enter the reset state. it may be desirable to provide an external pull-up and/or decou - pling of the /rst pin to avoid erroneou s noise-induced resets. the mcu will remain in reset until at least 12 clock cycles after the active-low /rst signal is removed. the pinrsf flag (rstsrc. 0) is set on exit from an external reset. 13.4. software forced reset writing a ?1? to the swrsef bit forces a software reset as described in section 13.1 . 13.5. missing clock detector reset the missing clock detector is essentially a one-shot circuit that is triggered by the mcu system clock. if the system clock goes away fo r more than 100 s, the one-shot will time out and generate a reset. after a missing clock detector reset, the mcdrsf flag (rstsrc.2) will be set, signifying th e msd as the reset source; othe rwise, this bit reads ?0?. the state of the /rst pin is unaffected by this reset. setting the msclke bit in the oscicn register (see section ? 14. oscillators ? on page 135 ) enables the missing clock detector. 13.6. comparator0 reset comparator0 can be configured as a reset input by writ ing a ?1? to the c0rsef fl ag (rstsrc.5). comparator0 should be enabled using cpt0cn.7 (see section ? 11. comparators ? on page 95 ) prior to writing to c0rsef to prevent any turn-on chatter on the output from generating an unwanted reset. the comparator0 reset is active-low: if the non-inverting input voltage (cp0+ pin) is less than the inverting input voltage (cp0- pin), the mcu is put into the reset state. after a comparator0 reset, the c0rsef flag (rstsrc.5) will read ?1? signifying comparator0 as the reset source; otherwise, this bit reads ?0?. the st ate of the /rst pin is unaffected by this reset. 13.7. external cnvstr pin reset the external cnvstr signal can be configured as a re set input by writing a ?1? to the cnvrsef flag (rstsrc.6). the cnvstr signal can appear on any of the p0, p1, p2 or p3 i/o pins as described in section ? 17.1. ports 0 through 3 and the priority crossbar decoder ? on page 163 . note that the crossbar mu st be configured for the cnvstr signal to be routed to the appr opriate port i/o. the cro ssbar should be configured and enabled before the cnvrsef is set. when configured as a reset, cnvstr is active-low and level sensitive. after a cnvstr reset, the cnvrsef flag (rstsrc.6) will read ?1? signifying cnvstr as the reset source; otherwise, this bit reads ?0?. the state of the /rst pin is unaffected by this reset. 13.8. watchdog timer reset the mcu includes a programmable watchdog timer (wdt) running off the system clock. a wdt overflow will force the mcu into the reset st ate. to prevent the reset, the wdt must be restarted by application software before overflow. if the system experiences a software/hardwar e malfunction preventing the software from restarting the wdt, the wdt will overflow and cause a reset. this should prevent the system from running out of control. following a reset the wdt is automatically enabled and runn ing with the default maximum time interval. if desired the wdt can be disabled by system so ftware or locked on to prevent accide ntal disabling. once locked, the wdt cannot be disabled until the next system reset. the st ate of the /rst pin is unaffected by this reset. the wdt consists of a 21-bit timer running from the programmed system clock. the timer measures the period between specific writes to its control re gister. if this period ex ceeds the programmed limit, a wdt reset is generated. the wdt can be enabled and disabled as needed in software, or can be perm anently enabled if desired. watchdog features are controlled via the watchdog timer control register (wdtcn) shown in figure 13.3 .
c8051f020/1/2/3 130 rev. 1.4 13.8.1. enable/reset wdt the watchdog timer is both enabled and reset by writing 0xa5 to the wdtcn register. the user's application soft - ware should include periodic writes of 0xa5 to wdtcn as needed to prevent a watchdog timer overflow. the wdt is enabled and reset as a result of any system reset. 13.8.2. disable wdt writing 0xde followed by 0xad to the wdtcn register disables the wdt. the following code segment illustrates disabling the wdt: clr ea ; disable all interrupts mov wdtcn,#0deh ; disable software watchdog timer mov wdtcn,#0adh setb ea ; re-enable interrupts the writes of 0xde and 0xad must occur within 4 clock cycles of each other, or the disable operation is ignored. interrupts should be disabled during this pro cedure to avoid delay between the two writes. 13.8.3. disable wdt lockout writing 0xff to wdtcn locks out the disable feature. once locked out, the disable operation is ignored until the next system reset. writing 0xff does not enable or reset the watchdog timer. applications always intending to use the watchdog should write 0xff to wdtcn in the initialization code. 13.8.4. setting wdt interval wdtcn.[2:0] control the watchdog timeout interval. the interval is given by the following equation: ; where t sysclk is the system clock period. for a 2 mhz system clock, this provides an interval range of 0.032 ms to 524 ms. wdtcn.7 must be logic 0 when setting this interval. reading wdtcn returns the programmed interval. wdtcn.[2:0] reads 111b after a system reset. 4 3 wdtcn 20 ? [] + t sysclk
c8051f020/1/2/3 rev. 1.4 131 bits7-0: wdt control writing 0xa5 both enables and reloads the wdt. writing 0xde followed within 4 system clocks by 0xad disables the wdt. writing 0xff locks out the disable feature. bit4: watchdog status bit (when read) reading the wdtcn.[4] bit indicates the watchdog timer status. 0: wdt is inactive 1: wdt is active bits2-0: watchdog timeout interval bits the wdtcn.[2:0] bits set the watchdog timeout interval. when writing these bits, wdtcn.7 must be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w reset value xxxxx111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xff figure 13.3. wdtcn: watchd og timer control register
c8051f020/1/2/3 132 rev. 1.4 figure 13.4. rstsrc: reset source register (note: do not use read-modify-writ e operations on this register.) bit7: reserved. bit6: cnvrsef: convert start reset source enable and flag write: 0: cnvstr is not a reset source. 1: cnvstr is a rese t source (active low). read: 0: source of prior reset was not cnvstr. 1: source of prior reset was cnvstr. bit5: c0rsef: comparator0 reset enable and flag write: 0: comparator0 is not a reset source. 1: comparator0 is a re set source (active low). read: 0: source of prior re set was not comparator0. 1: source of prior reset was comparator0. bit4: swrsf: software reset force and flag write: 0: no effect. 1: forces an internal reset. /rst pin is not affected. read: 0: prior reset source was not a write to the swrsf bit. 1: prior reset source was a write to the swrsf bit. bit3: wdtrsf: watchdog timer reset flag 0: source of prior reset was not wdt timeout. 1: source of prior reset was wdt timeout. bit2: mcdrsf: missing clock detector flag 0: source of prior reset was not missing clock detector timeout. 1: source of prior reset was missing clock detector timeout. bit1: porsf: power-on reset force and flag write: 0: no effect. 1: forces a power-on reset. /rst is driven low. read: 0: source of prior reset was not por. 1: source of prior reset was por. bit0: pinrsf: hw pin reset flag 0: source of prior reset was not /rst pin. 1: source of prior reset was /rst pin. r r/w r/w r/w r r r/w r reset value - cnvrsef c0rsef swrsef wdtrsf mcdrsf porsf pinrsf variable bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xef
c8051f020/1/2/3 rev. 1.4 133 table 13.1. reset electrical characteristics -40c to +85c unless otherwise specified. parameter conditions min typ max units /rst output high voltage i oh = -3 ma vdd - 0.7 v /rst output low voltage i ol = 8.5 ma, vdd = 2.7 v to 3.6 v 0.6 v /rst input high voltage 0.7 x vdd v /rst input low voltage 0.3 x vdd /rst input leakage cu rrent /rst = 0.0 v 50 a vdd for /rst output valid 1.0 v av+ for /rst output valid 1.0 v vdd por threshold (v rst ) 2.40 2.55 2.70 v minimum /rst low time to generate a system reset 10 ns reset time delay /rst rising edge after vdd crosses v rst threshold 80 100 120 ms missing clock detector timeout time from last system clock to reset initiation 100 220 500 s
c8051f020/1/2/3 134 rev. 1.4 notes
c8051f020/1/2/3 rev. 1.4 135 14. oscillators each mcu includes an internal oscillator a nd an external oscillator drive circuit, either of which can generate the sys - tem clock. the mcus operate from the inte rnal oscillator after any reset. this internal oscillator can be enabled/dis - abled and its frequency can be set using the internal oscillator control register (oscicn) as shown in figure 14.1 . the internal oscillator's electri cal specifications are given in table 14.1 . both oscillators are disabled when the /rst pin is held low. the mcus can run from the internal oscillator perma - nently, or can switch to the external os cillator if desired using clksl bit in the oscicn register. the external oscil - lator requires an external resonator, crystal, capacitor, or rc network co nnected to the xtal1/xtal2 pins (see table 14.1 ). the oscillator circuit must be co nfigured for one of these sources in the oscxcn register. an external cmos clock can also provide the system clock; in this configuration, the xtal1 pin is used as the cmos clock input. the xtal1 and xtal2 pins are not 5v tolerant. figure 14.1. oscillator diagram osc internal clock generator sysclk input circuit oscxcn en xtlvld xoscmd2 xoscmd1 xoscmd0 xfcn2 xfcn1 xfcn0 oscicn msclke ifrdy clksl ioscen ifcn1 ifcn0 xtal1 xtal2 opt. 1 opt. 2 opt. 4 opt. 3 xtal1 xtal2 xtal1 xtal1 av+ agnd vdd av+
c8051f020/1/2/3 136 rev. 1.4 table 14.1. internal oscillator el ectrical characteristics vdd = 2.7v to 3.6v; t a = -40c to +85c parameter conditions min typ max units internal oscillator frequency oscicn.[1:0] = 00 oscicn.[1:0] = 01 oscicn.[1:0] = 10 oscicn.[1:0] = 11 1.5 3.1 6.2 12.3 2 4 8 16 2.4 4.8 9.6 19.2 mhz internal oscillator current consumption (from vdd) oscicn.2 = 1 200 a figure 14.2. oscicn: internal oscillator control register bit7: msclke: missing clock enable bit 0: missing clock detector disabled 1: missing clock detector enabled; reset triggered if clock is missing for more than 100 s bits6-5: unused. read = 00b, write = don't care bit4: ifrdy: internal oscillator frequency ready flag 0: internal oscillator frequency not running at speed specified by the ifcn bits. 1: internal oscillator frequency runni ng at speed specified by the ifcn bits. bit3: clksl: system clock source select bit 0: uses internal oscillator as system clock. 1: uses external oscill ator as system clock. bit2: ioscen: internal oscillator enable bit 0: internal oscillator disabled 1: internal oscillator enabled bits1-0: ifcn1-0: internal oscillator frequency control bits 00: internal oscillator ty pical frequency is 2 mhz. 01: internal oscillator ty pical frequency is 4 mhz. 10: internal oscillator ty pical frequency is 8 mhz. 11: internal oscillator typical frequency is 16 mhz. r/w r/w r/w r/w r/w r/w r/w r/w reset value msclke - - ifrdy clksl ioscen ifcn1 ifcn0 00010100 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb2
c8051f020/1/2/3 rev. 1.4 137 f i gure 14 . 3 . osc x c n: external o sc i llator c ontrol reg i ster bit7: xtlvld: crystal oscillator valid flag (valid only when xoscmd = 11x.) 0: crystal oscillator is unused or not yet stable 1: crystal oscillator is running and stable bits6-4: xoscmd2-0: external oscillator mode bits 00x: off. xtal1 pin is grounded internally. 010: system clock from external cmos clock on xtal1 pin. 011: system clock from external cmos clock on xtal1 pin divided by 2. 10x: rc/c oscillator mode with divide by 2 stage. 110: crystal oscillator mode 111: crystal oscillator mode with divide by 2 stage. bit3: reserved. read = undefined, write = don't care bits2-0: xfcn2-0: external oscillator frequency control bits 000-111: crystal mode (circuit from figure 14.1, option 1; xoscmd = 11x) choose xfcn value to match the crys tal or ceramic resonator frequency. rc mode (circuit from figure 14.1, option 2; xoscmd = 10x) choose oscillation frequency range where: f = 1.23(10 3 ) / (r * c), where f = frequency of oscillation in mhz c = capacitor value in pf r = pull-up resistor value in k ? c mode (circuit from figure 14.1, option 3; xoscmd = 10x) choose k factor (kf) for the oscillation frequency desired: f = kf / (c * av+), where f = frequency of oscillation in mhz c = capacitor value on xtal1, xtal2 pins in pf av+ = analog power supply on mcu in volts r/w r/w r/w r/w r/w r/w r/w r/w reset value xtlvld xoscmd2 xoscmd1 xoscmd0 - xfcn2 xfcn1 xfcn0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb1 xfcn crystal (xoscmd = 11x) rc (xoscmd = 10x) c (xoscmd = 10x) 000 f < 12 khz f < 25 khz k factor = 0.44 001 12 khz < f 30 khz 25 khz < f 50 khz k factor = 1.4 010 30 khz < f 95 khz 50 khz < f 100 khz k factor = 4.4 011 95 khz < f 270 khz 100 khz < f 200 khz k factor = 13 100 270 khz < f 720 khz 200 khz < f 400 khz k factor = 38 101 720 khz < f 2.2 mhz 400 khz < f 800 khz k factor = 100 110 2.2 mhz < f 6.7 mhz 800 khz < f 1.6 mhz k factor = 420 111 f > 6.7 mhz 1.6 mhz < f 3.2 mhz k factor = 1400
c8051f020/1/2/3 138 rev. 1.4 14.1. external crystal example if a crystal or ceramic resonator is used as an external os cillator source for the mcu, th e circuit should be as shown in figure 14.1 , option 1. the external oscillator frequency control va lue (xfcn) should be chosen from the crys - tal column of the table in figure 14.3 (oscxcn register). for example, an 11.0592 mhz crystal requires an xfcn setting of 111b. the crystal oscillator valid flag (xtlvld in register os cxcn) is set to logic 1 by hardware when the external crystal oscillator is running and stable. the xtlvld de tection circuit requires a startup time of at least 1 ms between enabling the oscillator and ch ecking the xtlvld bit. switching to the exte rnal oscillator before the crystal oscillator has stabilized can result in unpredictable behavior. the recommended procedure is: step 1. enable the external oscillator. step 2. wait at least 1 ms. step 3. poll for xtlvld => ?1?. step 4. switch the system cloc k to the external oscillator. important note: crystal oscillator circuits are qu ite sensitive to pcb layout. the crys tal should be placed as close as possible to the xtal pins on the device, as should the load ing capacitors on the crystal pins. the traces should be as short as possible and shielded with ground plane from any other traces whic h could introduce noise or interference. 14.2. external rc example if an rc network is used as an ex ternal oscillator source for the mcu, the circuit should be as shown in figure 14.1 , option 2. the capacitor must be no greater than 100 pf; however for small cap acitors (less than ~20 pf), the total capacitance may be dominated by pwb parasitic capacitance. to determine the required external oscillator fre - quency control value (xfcn) in the oscxcn register, firs t select the rc network value to produce the desired fre - quency of oscillation. if the frequency desired is 100 khz, let r = 246 k ? and c = 50 pf: f = 1.23( 10 3 ) / rc = 1.23 ( 10 3 ) / [ 246 * 50 ] = 0.1 mhz = 100 khz xfcn log 2 ( f / 25 khz ) xfcn log 2 ( 100 khz / 25 khz ) = log 2 ( 4 ) xfcn 2, or code 010b 14.3. external capacitor example if a capacitor is used as an ex ternal oscillator for the mcu, th e circuit should be as shown in figure 14.1 , option 3. the capacitor must be no greater than 100 pf; however for small capacitors (less than ~20 pf), the total capacitance may be dominated by pwb parasitic capacitance. to dete rmine the required external oscillator frequency control value (xfcn) in the oscxcn register, select the capacitor to be used and find the frequency of oscillation from the equations below. assume vdd = 3.0 v and c = 50 pf: f = kf / ( c * vdd ) = kf / ( 50 * 3 ) f = kf / 150 if a frequency of roughly 90 khz is desired, select the k factor from the table in figure 14.3 as kf = 13: f = 13 / 150 = 0.087 mhz, or 87 khz therefore, the xfcn value to use in this example is 011b.
c8051f020/1/2/3 rev. 1.4 139 15. flash memory the c8051f020/1/2/3 family includes 64k + 128 bytes of on-chip, reprogrammable flash memory for program code and non-volatile data storage. the flash memory can be programmed in-system, a single byte at a time, through the jtag interface or by software. once cleared to lo gic 0, a flash bit must be erased to set it back to logic 1. the bytes would typically be erased (set to 0xff) before being reprogrammed. flash write and erase oper - ations are automatically timed by hardwa re for proper execution; data polling to determine the end of the write/erase operation is not required. refer to table 15.1 for the electrical characteri stics of the flash memory. 15.1. programming the flash memory the simplest means of programming the flash memory is through the jtag interface using programming tools provided by silicon labs or a third party vendor. this is the only means for programming a non-initialized device. for details on the jtag commands to program flash memory, see section ?24.2. flash programming com - mands? on page 268 . the flash memory can be programmed by software using a movx write instruction, with the address and data byte to be programmed provided as normal operands. before writing to flash memory using a movx write, flash write operations must be enabled by setting the pswe program store write enable bit (psctl.0) to logic 1. this directs the movx writes to flash memory instead of xram. the pswe bit remains set until cleared by soft - ware. to avoid errant flash writes, it is recommended that interrupts be disabled while the pswe bit is logic 1. flash memory is read using the movc read instruction. movx reads are always directed to xram, regardless of the state of pswe. to ensure the integrity of flash contents, it is st rongly recommended that the on-chip vdd monitor be enabled by tying the monen pin to v dd in any system which includes code that writes to or erases flash memory from software. a write to flash memory can clear bits but cannot set them; only an erase operatio n can set bits in flash. a byte location to be programmed must be erased before a new value can be written. the 64k byte flash memory is organized in 512-byte pages. the erase operation applies to an entire page (setting all bytes in the page to 0xff). the following steps illustrate the algorithm for programming flash by user software. step 1. disable interrupts. step 2. set flwe (flscl.0) to enable flash writes/erases via user software. step 3. set psee (psctl.1 ) to enable flash erases. step 4. set pswe (psctl.0) to redire ct movx commands to write to flash. step 5. use the movx command to wr ite a data byte to any location within the 512-byte page to be erased. step 6. clear psee to disable flash erases step 7. use the movx command to write a data byte to the desired byte location within the erased 512-byte page. repeat this step until all desired bytes are written (within the target page). step 8. clear the pswe bit to redir ect movx commands to the xram data space. step 9. re-enable interrupts.
c8051f020/1/2/3 140 rev. 1.4 write/erase timing is automatically controlled by hardware. note that code execution in the 8051 is stalled while the flash is being programmed or erased. interrupts th at are posted during a flash wr ite or erase operation are held pending until the flash operation has completed, at which time they are serviced by the cpu in priority order. 15.2. non-volatile data storage the flash memory can be used for non-vol atile data storage as well as program code. this allows data such as cal - ibration coefficients to be calculated an d stored at run time. data is written using the movx write instruction (as described in the previous section) and read using the movc read instruction. an additional 128-byte sector of flash memory is include d for non-volatile data storag e. its smaller sector size makes it particularly well suited as general purpose, non-volatile scratchpa d memory. even though flash memory can be written a single byte at a time, an en tire sector must be erased first. in order to chan ge a single byte of a multi- byte data set, the data must be moved to temporary storage. the 128-byte sector-size facilitates updating data without wasting program memory or ra m space. the 128-byte sector is double-mapped over the 64k byte flash memory; its address ranges from 0x00 to 0x7f (see figure 15.1 ). to access this 128-byte sector, the sfle bit in psctl must be set to logic 1. code execution from this 128-byte scratchpad sector is not permitted. 15.3. security options the cip-51 provides security options to protect the flash memory from inadvertent modification by software as well as prevent the viewing of proprietary program code and constants. the program st ore write enable (psctl.0) and the program store erase enable (psctl.1) bits protect the flash memory from accidental modification by software. these bits must be explicitly set to logic 1 before software can modify the flash memory. additional security features prevent pr oprietary program code and data constants from being read or altered across the jtag interface or by software runni ng on the system controller. a set of security lock bytes stored at 0xfdfe and 0xfdf f protect the flash program memory from being read or altered across the jtag interface. each bit in a security lock-byte protects one 8k-byte block of memory. clearing a bit to logic 0 in a read lock byte prevents the corresponding block of flash memory from being read across the jtag interface. clearing a bit in the write /erase lock byte protects the block fr om jtag erasures and/or writes. the 128-byte scratchpad sector is locked only when all other sectors are locked. the read lock byte is at location 0xfdff. the write/erase lock byte is located at 0xfdfe. figure 15.1 shows the location and bit definitions of the security bytes. the 512-by te sector containing the lock bytes can be written to, but not erased by software. an attempted read of a read-locked byte returns undefined data. debugging code in a read- locked sector is not possible through the jtag port. table 15.1. flash electrical characteristics vdd = 2.7v to 3.6v; t a = -40c to +85c parameter conditions min typ max units endurance 20k 100k erase/write erase cycle time 10 12 14 ms write cycle time 40 50 60 s
c8051f020/1/2/3 rev. 1.4 141 the lock bits can always be read and cleared to logic 0 regardless of the secu rity setting applied to the block contain - ing the security bytes. this allows additional blocks to be protected after the block containing the security bytes has been locked. important note: the only means of removing a lo ck once set is to erase the entire program mem - ory space by performing a jtag erase operation (i.e. cannot be done in user firmware). addressing either security byte while performing a jt ag erase operation will au tomatically initiate erasu re of the entire pro - gram memory space (except for the reserved area). th is erasure can only be performed via jtag. if a non- security byte in the 0xfbff-0xfdff p age is addressed during the jtag erasure, only that page (including the security bytes) will be erased. the flash access limit security feature (see figure 15.1 ) protects proprietary program code and data from being read by software running on the c8051f020/1/2/3. this f eature provides support for oems that wish to program the 0xfe00 0xfdfe program/data memory space 0x0000 0xfdff read lock byte write/erase lock byte software read limit reserved 0xffff 0xfdfd sfle = 0 bit memory block 7 6 5 4 0xc000 - 0xdfff 0xe000 - 0xfdfd 0xa000 - 0xbfff 0x8000 - 0x9fff 3 2 1 0 0x4000 - 0x5fff 0x6000 - 0x7fff 0x2000 - 0x3fff 0x0000 - 0x1fff read and write/erase security bits. (bit 7 is msb.) 0x007f 0x0000 scratchpad memory (data only) sfle = 1 figure 15.1. flash program memory map and security bytes flash read lock byte bits7-0: each bit locks a corresponding block of memory. (bit7 is msb). 0: read operations are locked (disabled) for co rresponding block acro ss the jtag interface. 1: read operations are unlocked (enabled) fo r corresponding block across the jtag interface. flash write/erase lock byte bits7-0: each bit locks a corresponding block of memory. 0: write/erase operations are locked (disabled) for corresponding block across the jtag interface. 1: write/erase operations are unlocked (enabled ) for corresponding block across the jtag interface. note: when the highest block is locked, the security bytes ma y be written but not erased. flash access limit register (flacl) the content of this register is used as the high byte of the 16-bit software read limit address. this 16- bit read limit address value is calculated as 0xnn0 0 where nn is replaced by co ntent of this register on reset. software running at or above this a ddress is prohibited from using the movx and movc instructions to read, write, or er ase flash locations below this address. any attempts to read loca- tions below this limit will return the value 0x00.
c8051f020/1/2/3 142 rev. 1.4 mcu with proprietary value-added firmware before distri bution. the value-added firmware can be protected while allowing additional code to be programmed in remaining program memory space later. the software read limit (srl) is a 16-bit address that establishes two logical partitions in the program memory space. the first is an upper partition co nsisting of all the program memory locati ons at or above the srl address, and the second is a lower partition consisting of all the program memory locations starting at 0x0000 up to (but exclud - ing) the srl address. software in the upper partition can execute code in the lower partition, but is prohibited from reading locations in the lower partition using the movc instruction. (executing a movc instruction from the upper partition with a source address in the lower partition will always return a data value of 0x00.) software running in the lower partition can access locations in both the u pper and lower partition without restriction. the value-added firmware should be pl aced in the lower partition. on reset, control is passed to the value-added firmware via the reset vector. once the value-added firmware completes its initial execution, it branches to a predeter - mined location in the upper partition. if entry points are published, software running in the upper partition may exe - cute program code in the lower partition, but it cannot read the contents of the lower partition. parameters may be passed to the program code running in the lower partition e ither through the typical method of placing them on the stack or in registers before the call or by placing them in prescribed memory locations in the upper partition. the srl address is specified using the contents of the flash access register . the 16-bit srl address is calculated as 0xnn00, where nn is the contents of the srl security register. thus, the srl can be located on 256-byte bound - aries anywhere in program memory space. however, the 512- byte erase sector size essent ially requires that a 512 boundary be used. the contents of a non-initialized srl s ecurity byte is 0x00, there by setting the srl address to 0x0000 and allowing read access to all locati ons in program memory space by default. bits 7-0: flacl: flash access limit. this register holds the high byte of the 16-bit pr ogram memory read/write/erase limit address. the entire 16-bit access limit address va lue is calculated as 0xnn00 where nn is replaced by contents of flacl. a write to this register sets the flash a ccess limit. this register can only be written once after any reset. any subsequent writes are ignored until the next reset. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb7 figure 15.2. flacl: flash access limit
c8051f020/1/2/3 rev. 1.4 143 figure 15.3. flscl: flash memory control bit7: fose: flash one-shot timer enable this is the timer that turns off the sense amps after a flash read. 0: flash one-shot timer disabled. 1: flash one-shot timer enabled. bit6: frae: flash read always enable 0: flash reads per one-shot timer. 1: flash always in read mode. bits5-1: reserved. read = 00000b. must write 00000b. bit0: flwe: flash read/write enable this bit must be set to allow flash writes from user software. 0: flash writes disabled. 1: flash writes enabled. r/w r/w r/w r/w r/w r/w r/w r/w reset value fose frae reserved reserved reserved reserved reserved flwe 10000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb6
c8051f020/1/2/3 144 rev. 1.4 figure 15.4. psctl: program store read/write control bits7-3: unused. read = 00000b, write = don't care. bit2: sfle: scratchpad flash memory access enable. when this bit is set, flash reads and writes from us er software are directed to the 128-byte scratch- pad flash sector. when sfle is set to logic 1, flash accesses out of the addr ess range 0x00- 0x7f should not be attempted. reads/writes out of this range will yield unpredictable results. 0: flash access from user software directed to the 64k byte program/data flash sector. 1: flash access from us er software directed to the 128 byte scratchpad sector. bit1: psee: program store erase enable. setting this bit allows an entire page of the flash program memory to be erased provided the pswe bit is also set. after setting this bit, a write to flash memory using the movx instruction will erase the entire page that co ntains the location addressed by the movx instruction. the value of the data byte written does not matter. 0: flash program memory erasure disabled. 1: flash program memo ry erasure enabled. bit0: pswe: program store write enable. setting this bit allows writing a byte of data to the flash program memory using the movx instruction. the location must be erased before writing data. 0: write to flash program memory disabled. 1: write to flash program memory enabled. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - - - - sfle psee pswe 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8f
c8051f020/1/2/3 rev. 1.4 145 16. external data memory interface and on-chip xram the c8051f020/1/2/3 mcus include 4k bytes of on-chip ram mapped into the external data memory space (xram), as well as an external data memory interface wh ich can be used to access off-chip memories and memory- mapped devices connected to the gpio ports. the external memory sp ace may be accessed using the external move instruction (movx) and the data pointer (dptr), or using th e movx indirect addressing mode using r0 or r1. if the movx instruction is used with an 8-bit address operand (such as @r1), then the high byte of the 16-bit address is provided by the external memory interf ace control register (emi0cn, shown in figure 16.1 ). note: the movx instruction can also be used for writing to the flash memory. see section ?15. flash memory? on page 139 for details. the movx instruction accesses xram by default. the emif can be configured to appear on the lower i/o ports (p0-p3) or the upper i/o ports (p4-p7). 16.1. accessing xram the xram memory space is accessed using the movx instru ction. the movx instruction has two forms, both of which use an indirect addressing method. the first method uses the data pointer, dptr, a 16-bit register which con - tains the effective address of the xram location to be read or written. the second method uses r0 or r1 in combina - tion with the emi0cn register to generate the effective xr am address. examples of both of these methods are given below. 16.1.1. 16-bit movx example the 16-bit form of the movx instructio n accesses the memory location pointed to by the contents of the dptr reg - ister. the following series of instru ctions reads the value of the byte at address 0x1234 into the accumulator a: mov dptr, #1234h ; load dptr with 16-bit address to read (0x1234) movx a, @dptr ; load contents of 0x1234 into accumulator a the above example uses the 16- bit immediate mov instruction to set the c ontents of dptr. alternately, the dptr can be accessed through the sfr registers dph, which contains the upper 8-bits of dptr, and dpl, which contains the lower 8-bits of dptr. 16.1.2. 8-bit movx example the 8-bit form of the movx instruction uses the contents of the emi0cn sfr to determine the upper 8-bits of the effective address to be accessed and the cont ents of r0 or r1 to de termine the lower 8-bits of the effective address to be accessed. the following series of instructions read the contents of the byte at address 0x1234 into the accumulator a. mov emi0cn, #12h ; load high byte of address into emi0cn mov r0, #34h ; load low byte of address into r0 (or r1) movx a, @r0 ; load contents of 0x1234 into accumulator a
c8051f020/1/2/3 146 rev. 1.4 16.2. configuring the external memory interface configuring the external memory interface consists of four steps: 1. select emif on low ports (p3, p2, p1, and p0) or high ports (p7, p6, p5, and p4). 2. select multiplexed mode or non-multiplexed mode. 3. select the memory mode (on-chip only, split mode without bank select, split mode with bank select, or off-chip only). 4. set up timing to interface with off-chip memory or peripherals. 5. select the desired output mode for the asso ciated ports (registe rs pnmdout, p74out). each of these four steps is explained in detail in the following sections. the port selection, multiplexed mode selec - tion, and mode bits are located in the emi0cf register shown in figure 16.2 . 16.3. port selection and configuration the external memory interface can appear on ports 3, 2, 1, and 0 (c8051f020/1/2/3 de vices) or on ports 7, 6, 5, and 4 (c8051f020/2 devices only), depending on the state of the prtsel bit (emi0cf.5). if th e lower ports are selected, the emifle bit (xbr2.1) must be set to a ?1? so that the cr ossbar will skip over p0.7 (/wr), p0.6 (/rd), and if mul - tiplexed mode is selected p0.5 (ale). for more information about the configuring the crossbar, see section ?17. port input/output? on page 161 . the external memory interface claims th e associated port pins for memory op erations only during the execution of an off-chip movx instruction. once the movx instruction has completed, control of the port pins reverts to the port latches or to the crossbar (on ports 3, 2, 1, and 0). see section ?17. port input/output? on page 161 for more information about the crossbar and port operation and configuration. the port latches should be explicitly configured to ?park? the external mem ory interface pins in a dormant stat e, most commonly by setting them to a logic 1 . during the execution of the movx instru ction, the external memory interface will explicitly disa ble the drivers on all port pins that are acting as inputs (data[7:0] during a re ad operation, for ex ample). the output mode of the port pins (whether the pin is configured as open-drain or push-pull) is unaffect ed by the external memory interface oper - ation, and remains controlled by the pnmdout registers. see section ?17. port input/output? on page 161 for more information about port output mode configuration.
c8051f020/1/2/3 rev. 1.4 147 figure 16.1. emi0cn: external memory interface control bits7-0: pgsel[7:0]: xram page select bits. the xram page select bits provide the high byte of the 16-bit external data memory address when using an 8-bit movx comma nd, effectively selecting a 256-byte page of ram. 0x00: 0x0000 to 0x00ff 0x01: 0x0100 to 0x01ff ... 0xfe: 0xfe00 to 0xfeff 0xff: 0xff00 to 0xffff r/w r/w r/w r/w r/w r/w r/w r/w reset value pgsel7 pgsel6 pgsel5 pgsel4 pgs el3 pgsel2 pgsel1 pgsel0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xaf figure 16.2. emi0cf: external memory configuration bits7-6: unused. read = 00b. write = don?t care. bit5: prtsel: emif port select. 0: emif active on p0-p3. 1: emif active on p4-p7. bit4: emd2: emif multiplex mode select. 0: emif operates in multiplexed address/data mode. 1: emif operates in non-multiplexed mode (separate address and data pins). bits3-2: emd1-0: emif operating mode select. these bits control the operating mode of the external memory interface. 00: internal only: movx accesses on-chip xram onl y. all effective addresses alias to on-chip memory space. 01: split mode without bank sel ect: accesses below the 4k boundary are directed on-chip. accesses above the 4k boundary are directed off-chip. 8-bit of f-chip movx operations use the current contents of the address high port la tches to resolve upper address byte. no te that in order to access off-chip space, emi0cn must be set to a page that is not contained in the on-chip address space. 10: split mode with bank select: accesses belo w the 4k boundary are directed on-chip. accesses above the 4k boundary are directed off-chip. 8-b it off-chip movx operations use the contents of emi0cn to determine the high-byte of the address. 11: external only: movx accesses off-chip xram on ly. on-chip xram is not visible to the cpu. bits1-0: eale1-0: ale pulse-width select bits (only has effect when emd2 = 0). 00: ale high and ale low pulse width = 1 sysclk cycle. 01: ale high and ale low pulse width = 2 sysclk cycles. 10: ale high and ale low pulse width = 3 sysclk cycles. 11: ale high and ale low pulse width = 4 sysclk cycles. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - prtsel emd2 emd1 emd0 eale1 eale0 00000011 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa3
c8051f020/1/2/3 148 rev. 1.4 16.4. multiplexed and non- multiplexed selection the external memory interface is capable of acting in a multiplexed mode or a no n-multiplexed mode, depending on the state of the em d2 (emi0cf.4) bit. 16.4.1. multiplexed configuration in multiplexed mode, the data bus and the lower 8-bits of the address bus share the same port pins: ad[7:0]. in this mode, an external latch (74hc373 or equivalent logic gate) is used to hold the lower 8-bits of the ram address. the external latch is controlled by the ale (address latch enable) signal, which is driven by the external memory inter - face logic. an example of a multip lexed configuration is shown in figure 16.3 . in multiplexed mode, the external movx operation can be broken into two phas es delineated by the state of the ale signal. during the first phase, ale is high and the lower 8-bits of the address bus are presented to ad[7:0]. during this phase, the address latch is config ured such that the ?q? outputs reflect the states of the ?d? inputs. when ale falls, signaling the beginning of the second phase, the address latch outputs remain fixed and are no longer dependent on the latch inputs. later in the second phase, the data bus controls the state of the ad[7: 0] port at the time /rd or /wr is asserted. see section ?16.6.2. multiplexed mode? on page 156 for more information. address/data bus address bus e m i f a[15:8] ad[7:0] /wr /rd ale 64k x 8 sram oe we i/o[7:0] 74hc373 g dq a[15:8] a[7:0] ce v dd 8 figure 16.3. multiplexed configuration example
c8051f020/1/2/3 rev. 1.4 149 16.4.2. non-multiplexed configuration in non-multiplexed mode, the data bus and the address bu s pins are not shared. an ex ample of a non-multiplexed configuration is shown in figure 16.4 . see section ?16.6.1. non-multiplexed mode? on page 153 for more infor - mation about non-multiplexed operation. address bus e m i f a[15:0] 64k x 8 sram a[15:0] data bus d[7:0] i/o[7:0] v dd 8 /wr /rd oe we ce figure 16.4. non-multiplexed configuration example
c8051f020/1/2/3 150 rev. 1.4 16.5. memory mode selection the external data memory space can be conf igured in one of f our modes, shown in figure 16.5 , based on the emif mode bits in the emi0cf register ( figure 16.2 ). these modes are summarized be low. more information about the different modes can be found in section ? .? on page 152 . 16.5.1. internal xram only when emi0cf.[3:2] are set to ?00?, all movx instructions will target the internal xram space on the device. mem - ory accesses to addresses beyond the populated space will wr ap on 4k boundaries. as an example, the addresses 0x1000 and 0x2000 bot h evaluate to address 0x0000 in on-chip xram space. ? 8-bit movx operations use the contents of emi0cn to de termine the high-byte of th e effective address and r0 or r1 to determine the low- byte of the effective address. ? 16-bit movx operations use the contents of the 16-bit dptr to determine the effective address. 16.5.2. split mode without bank select when emi0cf.[3:2] are set to ?01?, th e xram memory map is split into two areas, on-chip space a nd off-chip space. ? effective addresses below the 4k boundary will access on -chip xram space. ? effective addresses beyond the 4k boundary will access off-chip space. ? 8-bit movx operations use the contents of emi0cn to determ ine whether the memory access is on-chip or off- chip. the lower 8-bits of the address bus a[7:0] are driven as defined by r0 or r1. however, in the ?no bank select? mode, an 8-bit movx operation will not drive th e upper 8-bits a[15:8] of the address bus during an off-chip access. this allows the user to manipulate the upper address bits at will by setting the port state directly. this behavior is in contrast with ?split mode with bank select? described below. ? 16-bit movx operations use the contents of dptr to determine whether the memory access is on-chip or off- chip, and unlike 8-bit movx operations, the full 16-bits of the address bus a[15:0] are driven during the off- chip transaction. emi0cf[3:2] = 00 0xffff 0x0000 emi0cf[3:2] = 11 0xffff 0x0000 emi0cf[3:2] = 01 0xffff 0x0000 emi0cf[3:2] = 10 on-chip xram on-chip xram on-chip xram on-chip xram on-chip xram on-chip xram off-chip memory (no bank select) on-chip xram 0xffff 0x0000 off-chip memory (bank select) on-chip xram off-chip memory figure 16.5. emif operating modes
c8051f020/1/2/3 rev. 1.4 151 16.5.3. split mode with bank select when emi0cf.[3:2] are set to ?10?, th e xram memory map is split into two areas, on-chip space a nd off-chip space. ? effective addresses below the 4k boundary will access on -chip xram space. ? effective addresses beyond the 4k boundary will access off-chip space. ? 8-bit movx operations use the contents of emi0cn to determ ine whether the memory access is on-chip or off- chip. the upper 8-bits of the address bus a[15:8] ar e determined by emi0cn, and the lower 8-bits of the address bus a[7:0] are determined by r0 or r1. all 16 -bits of the address bus a[ 15:0] are driven in ?bank select? mode. ? 16-bit movx operations use the contents of dptr to determine whether the memory access is on-chip or off- chip, and the full 16-bits of th e address bus a[15:0] are driven during the off-chip transaction. 16.5.4. external only when emi0cf[3:2] are set to ?11?, all movx operations are directed to off- chip space. on-chip xram is not visi - ble to the cpu. this mode is useful for accessing off-c hip memory located between 0x0000 and the 4k boundary. ? 8-bit movx operations ignore the contents of emi0cn. the upper address bits a[15:8] are not driven (identi - cal behavior to an off-chip access in ?split mode without bank select? described above). this allows the user to manipulate the upper address bits at will by setting th e port state directly. the lo wer 8-bits of the effective address a[7:0] are determined by the contents of r0 or r1. ? 16-bit movx operations use the contents of dptr to de termine the effective addres s a[15:0]. the full 16-bits of the address bus a[15:0] are driv en during the off- chip transaction. 16.6. timing the timing parameters of the external memory interface can be configured to enable c onnection to devices having different setup and hold time requirements. the address setup time, address hold time, /rd and /wr strobe widths, and in multiplexed mode, the width of the ale pulse ar e all programmable in units of sysclk periods through emi0tc, shown in figure 16.6 , and emi0cf[1:0]. the timing for an off-chip movx instruction can be calculate d by adding 4 sysclk cycles to the timing parameters defined by the emi0tc register. assuming non-multiplexed operation, the minimum execution time for an off-chip xram operation is 5 sysclk cycles (1 sysclk for /rd or /wr pulse + 4 sysclks). for multiplexed opera - tions, the address latch enable signal will require a mini mum of 2 additional sysclk cycles. therefore, the mini - mum execution time of an off-chip xram operation in mu ltiplexed mode is 7 sysclk cycles (2 sysclks for /ale, 1 for /rd or /wr + 4 sysclks). the programmable setup and hold times default to the maximum delay set - tings after a reset. table 16.1 lists the ac parameters for the external memory interface, and figure 16.7 through figure 16.11 show the timing diagrams for the different external memory interface modes and movx operations
c8051f020/1/2/3 152 rev. 1.4 . figure 16.6. emi0tc: extern al memory timing control bits7-6: eas1-0: emif address setup time bits. 00: address setup time = 0 sysclk cycles. 01: address setup time = 1 sysclk cycle. 10: address setup time = 2 sysclk cycles. 11: address setup time = 3 sysclk cycles. bits5-2: ewr3-0: emif /wr and /rd pulse-width control bits. 0000: /wr and /rd pulse width = 1 sysclk cycle. 0001: /wr and /rd pulse width = 2 sysclk cycles. 0010: /wr and /rd pulse width = 3 sysclk cycles. 0011: /wr and /rd pulse width = 4 sysclk cycles. 0100: /wr and /rd pulse width = 5 sysclk cycles. 0101: /wr and /rd pulse width = 6 sysclk cycles. 0110: /wr and /rd pulse width = 7 sysclk cycles. 0111: /wr and /rd pulse width = 8 sysclk cycles. 1000: /wr and /rd pulse width = 9 sysclk cycles. 1001: /wr and /rd pulse width = 10 sysclk cycles. 1010: /wr and /rd pulse width = 11 sysclk cycles. 1011: /wr and /rd pulse width = 12 sysclk cycles. 1100: /wr and /rd pulse width = 13 sysclk cycles. 1101: /wr and /rd pulse width = 14 sysclk cycles. 1110: /wr and /rd pulse width = 15 sysclk cycles. 1111: /wr and /rd pulse width = 16 sysclk cycles. bits1-0: eah1-0: emif address hold time bits. 00: address hold time = 0 sysclk cycles. 01: address hold time = 1 sysclk cycle. 10: address hold time = 2 sysclk cycles. 11: address hold time = 3 sysclk cycles. r/w r/w r/w r/w r/w r/w r/w r/w reset value eas1 eas0 ewr3 ewr2 ewr1 ewr0 eah1 eah0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa1
c8051f020/1/2/3 rev. 1.4 153 16.6.1. non-multiplexed mode 16.6.1.1. 16-bit movx: emi0cf[4:2 ] = ?101?, ?110?, or ?111?. emif address (8 msbs) from dph emif address (8 lsbs) from dpl p2/p6 p1/p5 p0.7/p4.7 p0.6/p4.6 p3/p7 emif write data p2/p6 p1/p5 p0.7/p4.7 p0.6/p4.6 p3/p7 t ach t wdh t acw t acs t wds addr[15:8] addr[7:0] data[7:0] /wr /rd emif address (8 msbs) from dph emif address (8 lsbs) from dpl p2/p6 p1/p5 p0.6/p4.6 p0.7/p4.7 p3/p7 p2/p6 p1/p5 p0.6/p4.6 p0.7/p4.7 p3/p7 t ach t rdh t acw t acs t rds addr[15:8] addr[7:0] data[7:0] /rd /wr emif read data nonmuxed 16-bit write nonmuxed 16-bit read figure 16.7. non-multiplexed 16-bit movx timing
c8051f020/1/2/3 154 rev. 1.4 16.6.1.2. 8-bit movx without bank se lect: emi0cf[4:2] = ?101? or ?111?. emif address (8 lsbs) from r0 or r1 p2/p6 p1/p5 p0.7/p4.7 p0.6/p4.6 p3/p7 emif write data p2/p6 p0.7/p4.7 p0.6/p4.6 p3/p7 t ach t wdh t acw t acs t wds addr[15:8] addr[7:0] data[7:0] /wr /rd emif address (8 lsbs) from r0 or r1 p2/p6 p1/p5 p0.6/p4.6 p0.7/p4.7 p3/p7 p2/p6 p0.6/p4.6 p0.7/p4.7 p3/p7 t ach t rdh t acw t acs t rds addr[15:8] addr[7:0] data[7:0] /rd /wr emif read data nonmuxed 8-bit write without bank select nonmuxed 8-bit read without bank select figure 16.8. non-multiplexed 8-bit movx without bank select timing
c8051f020/1/2/3 rev. 1.4 155 16.6.1.3. 8-bit movx with bank select: emi0cf[4:2] = ?110?. emif address (8 msbs) from emi0cn emif address (8 lsbs) from r0 or r1 p2/p6 p1/p5 p0.7/p4.7 p0.6/p4.6 p3/p7 emif write data p2/p6 p1/p5 p0.7/p4.7 p0.6/p4.6 p3/p7 t ach t wdh t acw t acs t wds addr[15:8] addr[7:0] data[7:0] /wr /rd emif address (8 msbs) from emi0cn emif address (8 lsbs) from r0 or r1 p2/p6 p1/p5 p0.6/p4.6 p0.7/p4.7 p3/p7 p2/p6 p1/p5 p0.6/p4.6 p0.7/p4.7 p3/p7 t ach t rdh t acw t acs t rds addr[15:8] addr[7:0] data[7:0] /rd /wr emif read data nonmuxed 8-bit write with bank select nonmuxed 8-bit read with bank select figure 16.9. non-multiplexed 8-bi t movx with bank select timing
c8051f020/1/2/3 156 rev. 1.4 16.6.2. multiplexed mode 16.6.2.1. 16-bit movx: emi0cf[4:2 ] = ?001?, ?010?, or ?011?. p3/p7 p2/p6 p3/p7 addr[15:8] ad[7:0] p2/p6 p0.7/p4.7 p0.6/p4.6 p0.5/p4.5 p0.7/p4.7 p0.6/p4.6 p0.5/p4.5 t ach t wdh t acw t acs t wds ale /wr /rd emif address (8 msbs) from dph emif write data emif address (8 lsbs) from dpl t aleh t alel p3/p7 p2/p6 p3/p7 addr[15:8] ad[7:0] p2/p6 p0.6/p4.6 p0.7/p4.7 p0.5/p4.5 p0.6/p4.6 p0.7/p4.7 p0.5/p4.5 t ach t acw t acs ale /rd /wr emif address (8 msbs) from dph emif address (8 lsbs) from dpl t aleh t alel t rdh t rds emif read data muxed 16-bit write muxed 16-bit read figure 16.10. multiplexed 16-bit movx timing
c8051f020/1/2/3 rev. 1.4 157 16.6.2.2. 8-bit movx without bank se lect: emi0cf[4:2] = ?001? or ?011?. p3/p7 p2/p6 p3/p7 addr[15:8] ad[7:0] p0.7/p4.7 p0.6/p4.6 p0.5/p4.5 p0.7/p4.7 p0.6/p4.6 p0.5/p4.5 t ach t wdh t acw t acs t wds ale /wr /rd emif write data emif address (8 lsbs) from r0 or r1 t aleh t alel p3/p7 p2/p6 p3/p7 addr[15:8] ad[7:0] p0.6/p4.6 p0.7/p4.7 p0.5/p4.5 p0.6/p4.6 p0.7/p4.7 p0.5/p4.5 t ach t acw t acs ale /rd /wr emif address (8 lsbs) from r0 or r1 t aleh t alel t rdh t rds emif read data muxed 8-bit write without bank select muxed 8-bit read without bank select figure 16.11. multiplexed 8-bit mo vx without bank select timing
c8051f020/1/2/3 158 rev. 1.4 16.6.2.3. 8-bit movx with bank select: emi0cf[4:2] = ?010?. p3/p7 p2/p6 p3/p7 addr[15:8] ad[7:0] p2/p6 p0.7/p4.7 p0.6/p4.6 p0.5/p4.5 p0.7/p4.7 p0.6/p4.6 p0.5/p4.5 t ach t wdh t acw t acs t wds ale /wr /rd emif address (8 msbs) from emi0cn emif write data emif address (8 lsbs) from r0 or r1 t aleh t alel p3/p7 p2/p6 p3/p7 addr[15:8] ad[7:0] p2/p6 p0.6/p4.6 p0.7/p4.7 p0.5/p4.5 p0.6/p4.6 p0.7/p4.7 p0.5/p4.5 t ach t acw t acs ale /rd /wr emif address (8 msbs) from emi0cn emif address (8 lsbs) from r0 or r1 t aleh t alel t rdh t rds emif read data muxed 8-bit write with bank select muxed 8-bit read with bank select figure 16.12. multiplexed 8-bit movx with bank select timing
c8051f020/1/2/3 rev. 1.4 159 table 16.1. ac parameters for external memory interface parameter description min max units t sysclk system clock period 40 ns t acs address / control setup time 0 3*t sysclk ns t acw address / control pulse width 1*t sysclk 16*t sysclk ns t ach address / control hold time 0 3*t sysclk ns t aleh address latch enable high time 1*t sysclk 4*t sysclk ns t alel address latch enable low time 1*t sysclk 4*t sysclk ns t wds write data setup time 1*t sysclk 19*t sysclk ns t wdh write data hold time 0 3*t sysclk ns t rds read data setup time 20 ns t rdh read data hold time 0 ns
c8051f020/1/2/3 160 rev. 1.4 notes
c8051f020/1/2/3 rev. 1.4 161 17. port input/output the c8051f020/1/2/3 are fully integrated mixed-signal system on a chip mcus with 64 digital i/o pins (c8051f020/2) or 32 digital i/o pins (c8051f021/3), organi zed as 8-bit ports. the lower ports: p0, p1, p2, and p3, are both bit- and byte-addressable through their correspondi ng port data registers. the upper ports: p4, p5, p6, and p7 are byte-addressable. all port pins are 5 v-tolerant, and all support configurable open-drain or push-pull output modes and weak pull-ups. a block diagram of the port i/o cell is shown in figure 17.1 . complete electrical specifi - cations for the port i/o pins are given in table 16.1 . tab le 17.1. port i/o dc electrical characteristics vdd = 2.7 v to 3.6 v, -40c to +85c unless otherwise specified. parameter conditions min typ max units output high voltage (v oh ) i oh = -10 a, port i/o push-pull i oh = -3 ma, port i/o push-pull i oh = -10 ma, port i/o push-pull vdd - 0.1 vdd - 0.7 vdd - 0.8 v output low voltage (v ol ) i ol = 10 a i ol = 8.5 ma i ol = 25 ma 1.0 0.1 0.6 v input high voltage (vih) 0.7 x vdd v input low voltage (vil) 0.3 x vdd v input leakage current dgnd < port pin < vdd, pin tri-state weak pull-up off weak pull-up on 10 1 a input capacitance 5 pf dgnd /port-outenable port-output push-pull vdd vdd /weak-pullup (weak) port pad analog input analog select (port 1 only) port-input figure 17.1. port i/o cell block diagram
c8051f020/1/2/3 162 rev. 1.4 the c8051f020/1/2/3 devices have a wide array of digital resources which are available through the four lower i/o ports: p0, p1, p2, and p3. each of the pins on p0, p1, p2, and p3, can be defined as a general-purpose i/o (gpio) pin or can be controlled by a digital peripheral or f unction (like uart0 or /int1 for example), as shown in figure 17.2 . the system designer controls which digital functions are assi gned pins, limited only by the number of pins available. this resource assignment flexibility is achieved through the us e of a priority crossbar decoder. note that the state of a port i/o pin can always be read from its associated data register regardless of whether that pin has been assigned to a digital peripheral or behaves as gpio. the port pins on port 1 can be used as an alog inputs to adc1. an external memory interface which is active during the execution of a movx instruction whose target address resides in off-chip memory can be active on e ither the lower ports or the upper ports. see section ?16. external data memory interface and on-chip xram? on page 145 for more informati on about the external memory interface. the upper ports (available on c8051f020 /2) can be byte-accessed as gpio pins. external pins digital crossbar priority decoder smbus 2 spi 4 uart0 2 pca 2 t0, t1, t2, t2ex, t4,t4ex /int0, /int1 p1.0 p1.7 p2.0 p2.7 p0.0 p0.7 highest priority lowest priority 8 8 comptr. outputs (internal digital signals) highest priority lowest priority uart1 /sysclk cnvstr 6 2 p3.0 p3.7 8 8 p0mdout, p1mdout, p2mdout, p3mdout registers xbr0, xbr1, xbr2, p1mdin registers p1 i/o cells p3 i/o cells p0 i/o cells p2 i/o cells 8 port latches p0 p1 p2 8 8 8 p3 8 (p2.0-p2.7) (p1.0-p1.7) (p0.0-p0.7) (p3.0-p3.7) to adc1 input to external memory interface (emif) figure 17.2. lower port i/o functional block diagram
c8051f020/1/2/3 rev. 1.4 163 17.1. ports 0 through 3 and the priority crossbar decoder the priority crossbar decoder, or ?crossbar ?, allocates and assigns port pins on port 0 through port 3 to the digital peripherals (uarts, smbus, pca, timers, etc.) on the device using a priority order. the port pins are allocated in order starting with p0.0 and continue through p3.7 if necessa ry. the digital peripherals are assigned port pins in a pri - ority order which is listed in figure 17.3 , with uart0 having the highest priority and cnvstr having the lowest priority. 17.1.1. crossbar pin assignment and allocation the crossbar assigns port pins to a peripheral if the corr esponding enable bits of the peripheral are set to a logic 1 in the crossbar configuration registers xbr0, xbr1, and xbr2, shown in figure 17.7 , figure 17.8 , and figure 17.9 . for example, if the uart0en bit (xbr0.2) is set to a logic 1, the tx0 and rx0 pins will be mapped to p0.0 and p0.1 respectively. because uart0 has the highest priority, its pins will always be mapped to p0.0 and p0.1 when uart0en is set to a logic 1. if a digital peripheral?s enab le bits are not set to a logic 1, then its ports are not accessi - ble at the port pins of the device. also note that the crossbar assigns pins to all associated functi ons when a serial communication peripheral is selected (i .e. smbus, spi, uart). it would be impossible, for example, to assign tx0 figure 17.3. priority crossbar decode table (emifle = 0; p1mdin = 0xff) pin i/o01234567012345670123456701234567 tx0 rx0 sck miso mosi nss sda scl tx1 rx1 cex0 cex1 cex2 cex3 cex4 eci eci0e: xbr0.6 cp0 cp0e: xbr0.7 cp1 cp1e: xbr1.0 t0 t0e: xbr1.1 /int0 int0e: xbr1.2 t1 t1e: xbr1.3 /int1 int1e: xbr1.4 t2 t2e: xbr1.5 t2ex t2exe: xbr1.6 t4 t4e: xbr2.3 t4ex t4exe: xbr2.4 /sysclk syscke: xbr1.7 cnvstr cnvste: xbr2.0 ale /rd /wr ain1.0/a8 ain1.1/a9 ain1.2/a10 ain1.3/a11 ain1.4/a12 ain1.5/a13 ain1.6/a14 ain1.7/a15 a8m/a0 a9m/a1 a10m/a2 a11m/a3 a12m/a4 a13m/a5 a14m/a6 a15m/a7 ad0/d0 ad1/d1 ad2/d2 ad3/d3 ad4/d4 ad5/d5 ad6/d6 ad7/d7 p0 p1 p2 p3 ain1 inputs/non-muxed addr h muxed addr h/non-muxed addr l muxed data/non-muxed data uart1en: pca0me: crossbar register bits xbr0.2 xbr0.1 xbr0.0 smb0en: xbr2.2 xbr0.[5:3] uart0en: spi0en:
c8051f020/1/2/3 164 rev. 1.4 to a port pin without assigning rx0 as well. each combin ation of enabled peripherals results in a unique device pinout. all port pins on ports 0 through 3 that are not allo cated by the crossbar can be accessed as general-purpose i/o (gpio) pins by reading and writing th e associated port data registers (see figure 17.10 , figure 17.12 , figure 17.15 , and figure 17.17 ), a set of sfrs which are both byte- and bit-addre ssable. the output states of port pins that are allo - cated by the crossbar are controlled by th e digital peripheral that is mapped to those pins. writes to the port data reg - isters (or associated port bits) will have no effect on the states of these pins. a read of a port data register (or port bit) will always re turn the logic state present at the pin itself, regardless of whether the crossbar has allocated the pi n for peripheral use or not. an excep tion to this occurs during the execution of a read-modify-write instruction (anl, orl, xrl, cpl, inc, dec, djnz, jbc, clr, set, and the bitwise mov operation). during the read cycle of the read-modify-write instruction, it is the contents of the port data register, not the state of the port pins themselves, which is read. because the crossbar registers affect th e pinout of the peripherals of the device, they are typically configured in the initialization code of the system before the peripherals th emselves are configured. once configured, the crossbar reg - isters are typically left alone. once the crossbar registers have been properly configured, the cr ossbar is enabled by setting xbare (xbr2.6) to a logic 1. until xbare is set to a logic 1, the output drivers on ports 0 through 3 are explicitly disabled in order to prevent possible contenti on on the port pins while the crossbar registers and other registers which can affect the device pino ut are being written . the output drivers on crossbar-assigned input signals (like rx 0, for example) are explicitly disabled; thus the values of the port data registers and the pnmdout regist ers have no effect on the states of these pins. 17.1.2. configuring the output modes of the port pins the output drivers on ports 0 through 3 remain disabled until the crossbar is enabled by setting xbare (xbr2.6) to a logic 1. the output mode of each port pin can be configured as eith er open-drain or push-pull; the default state is open- drain. in the push-pull configuration, writing a logic 0 to the associated bit in the po rt data register will cause the port pin to be driven to gnd, and writing a logic 1 will cause the port pin to be driven to vdd. in the open-drain configuration, writing a logic 0 to the associated bit in the port data regist er will cause the port pin to be driven to gnd, and a logic 1 will cause the port pin to assume a high-impedance state. the open-drain configuration is useful to prevent contention between devices in systems where the port pin participates in a shared interconnection in which multiple outputs are connected to the same physical wire (like th e sda signal on an smbus connection). the output modes of the port pins on ports 0 through 3 are determined by the bits in the associated pnmdout regis - ters (see figure 17.11 , figure 17.14 , figure 17.16 , and figure 17.18 ). for example, a logic 1 in p3mdout.7 will configure the output mode of p3.7 to push-pull; a logic 0 in p3mdout.7 will configure the output mode of p3.7 to open-drain. all port pins default to open-drain output. the pnmdout registers control the output modes of the por t pins regardless of whether the crossbar has allocated the port pin for a digital peripheral or not. the exceptions to this rule are: th e port pins connected to sda, scl, rx0 (if uart0 is in mode 0), and rx1 (if uart1 is in mode 0) are always configured as op en-drain outputs, regardless of the settings of the associated bits in the pnmdout registers.
c8051f020/1/2/3 rev. 1.4 165 17.1.3. configuring port pins as digital inputs a port pin is configured as a digital input by settin g its output mode to ?open-drain? and writing a logic 1 to the associated bit in the port data register . for example, p3.7 is configured as a digital input by setting p3mdout.7 to a logic 0 and p3.7 to a logic 1. if the port pin has been assign ed to a digital peripheral by th e crossbar and that pin functions as an input (for example rx0, the uart0 receive pin), then the output dr ivers on that pin are automatically disabled. 17.1.4. external interrupts (ie6 and ie7) in addition to the external interrupts /int0 and /int1, wh ose port pins are allocated and assigned by the crossbar, p3.6 and p3.7 can be configured to generate edge sensitive interrupts; these interrupts are configurable as falling- or rising-edge sensitive using the ie6cf (p3i f.2) and ie7cf (p3if.3) bits. when an active edge is detected on p3.6 or p3.7, a corresponding external interrupt flag (ie6 or ie7) will be set to a logic 1 in the p3if register (see figure 17.19 ). if the associated interrupt is enabled, an interrupt will be generated and the cpu will vector to the associated interrupt vector location. see section ?12.3. interrupt handler? on page 116 for more information about interrupts. 17.1.5. weak pull-ups by default, each port pin has an internal weak pull-up device enabled which provides a resistive connection (about 100 k ? ) between the pin and vdd. the weak pull-up devices can be globally disabled by writing a logic 1 to the weak pull-up disable bit, (weakpud, x br2.7). the weak pull-up is automati cally deactivated on any pin that is driving a logic 0; that is, an output pin will not contend with it s own pull-up device. the weak pull-up device can also be explicitly disabled on a port 1 pin by configuring the pin as an analog input, as described below. 17.1.6. configuring port 1 pins as analog inputs (ain1.[7:0]) the pins on port 1 can serve as analog inputs to the adc1 analog mu x. a port pin is configur ed as an analog input by writing a logic 0 to the associated bit in the p1mdin register (see figure 17.13 ). all port pins default to a digital input mode. configuring a port pin as an analog input: 1. disables the digital input path from the pin. this prevents additional power supply current from being drawn when the vo ltage at the pin is near vdd / 2. a read of the port data bit will return a logic 0 regardless of the voltage at the port pin. 2. disables the weak pull-up device on the pin. 3. causes the crossbar to ?skip over? the pin when allocating port pins for digital peripherals. note that the output drivers on a pin configured as an analog input are not explicitly disabled. therefore, the associated p1mdout bits of pins configured as analog inputs should explicitly be set to logic 0 (open-drain output mode), and the associated port da ta bits should be set to logic 1 (high-impedance). also note that it is not required to configure a port pin as an analog input in order to use it as an input to the adc1 mux; however, it is strongly rec - ommended. see section ?7. adc1 (8-bit adc)? on page 75 for more information about adc1.
c8051f020/1/2/3 166 rev. 1.4 17.1.7. external memory interface pin assignments if the external memory interface (emif) is enabled on the low ports (ports 0 through 3), emifle (xbr2.1) should be set to a logic 1 so that the crossbar will not assign peripherals to p0.7 (/wr), p0.6 (/rd), and if the external mem - ory interface is in multiplexed mode, p0.5 (ale). figure 17.4 shows an example crossbar decode table with emifle=1 and the emif in multiplexed mode. figure 17.5 shows an example crossb ar decode table with emifle=1 and the emif in n on-multiplexed mode. if the external memory interface is en abled on the low ports and an off-chip movx operation occurs, the external memory interface will control the output states of the affected port pins during the execution phase of the movx instruction, regardless of the settings of the crossbar regist ers or the port data registers. the output configuration of the port pins is not affected by the em if operation, except that read operati ons will explicitly disable the output drivers on the data bus. see section ?16. external data memory interface and on-chip xram? on page 145 for more information about the external memory interface. pin i/o01234567012345670123456701234567 tx0 rx0 sck miso mosi nss sda scl tx1 rx1 cex0 cex1 cex2 cex3 cex4 eci eci0e: xbr0.6 cp0 cp0e: xbr0.7 cp1 cp1e: xbr1.0 t0 t0e: xbr1.1 /int0 int0e: xbr1.2 t1 t1e: xbr1.3 /int1 int1e: xbr1.4 t2 t2e: xbr1.5 t2ex t2exe: xbr1.6 t4 t4e: xbr2.3 t4ex t4exe: xbr2.4 /sysclk syscke: xbr1.7 cnvstr cnvste: xbr2.0 ale /rd /wr ain1.0/a8 ain1.1/a9 ain1.2/a10 ain1.3/a11 ain1.4/a12 ain1.5/a13 ain1.6/a14 ain1.7/a15 a8m/a0 a9m/a1 a10m/a2 a11m/a3 a12m/a4 a13m/a5 a14m/a6 a15m/a7 ad0/d0 ad1/d1 ad2/d2 ad3/d3 ad4/d4 ad5/d5 ad6/d6 ad7/d7 xbr2.2 xbr0.[5:3] uart0en: spi0en: crossbar register bits xbr0.2 xbr0.1 xbr0.0 smb0en: ain1 inputs/non-muxed addr h muxed addr h/non-muxed addr l muxed data/non-muxed data uart1en: pca0me: p0 p1 p2 p3 figure 17.4. priority crossbar decode table emifle = 1; emif in multiplexed mode; p1mdin = 0xff)
c8051f020/1/2/3 rev. 1.4 167 figure 17.5. priority crossbar decode table (emifle = 1; emif in non-mu ltiplexed mode; p1mdin = 0xff) pin i/o01234567012345670123456701234567 tx0 rx0 sck miso mosi nss sda scl tx1 rx1 cex0 cex1 cex2 cex3 cex4 eci eci0e: xbr0.6 cp0 cp0e: xbr0.7 cp1 cp1e: xbr1.0 t0 t0e: xbr1.1 /int0 int0e: xbr1.2 t1 t1e: xbr1.3 /int1 int1e: xbr1.4 t2 t2e: xbr1.5 t2ex t2exe: xbr1.6 t4 t4e: xbr2.3 t4ex t4exe: xbr2.4 /sysclk syscke: xbr1.7 cnvstr cnvste: xbr2.0 ale /rd /wr ain1.0/a8 ain1.1/a9 ain1.2/a10 ain1.3/a11 ain1.4/a12 ain1.5/a13 ain1.6/a14 ain1.7/a15 a8m/a0 a9m/a1 a10m/a2 a11m/a3 a12m/a4 a13m/a5 a14m/a6 a15m/a7 ad0/d0 ad1/d1 ad2/d2 ad3/d3 ad4/d4 ad5/d5 ad6/d6 ad7/d7 xbr2.2 xbr0.[5:3] uart0en: spi0en: crossbar register bits xbr0.2 xbr0.1 xbr0.0 smb0en: ain1 inputs/non-muxed addr h muxed addr h/non-muxed addr l muxed data/non-muxed data uart1en: pca0me: p0 p1 p2 p3
c8051f020/1/2/3 168 rev. 1.4 17.1.8. crossbar pin assignment example in this example ( figure 17.6 ), we configure the crossbar to allocate port pins for uart0, the smbus, uart1, /int0, and /int1 (8 pins total). additionally, we co nfigure the external memory inte rface to operate in multiplexed mode and to appear on the low ports. further, we configure p1.2, p1.3, and p1.4 for analog input mode so that the voltages at these pins can be measured by adc 1. the configuration steps are as follows: 1. xbr0, xbr1, and xbr2 are set such that uar t0en = 1, smb0en = 1, int0e = 1, int1e = 1, and emifle = 1. thus: xbr0 = 0x05, xbr1 = 0x14, and xbr2 = 0x02. 2. we configure the external me mory interface to use multiplexe d mode and to appear on the low ports. prtsel = 0, emd2 = 0. 3. we configure the desired port 1 pins to analog input mode by setting p1mdin to 0xe3 (p1.4, p1.3, and p1.2 are analog inputs, so their associated p1mdin bits are set to logic 0). 4. we enable the crossbar by setting xbare = 1: xbr2 = 0x46. - uart0 has the highest priority, so p0.0 is assigned to tx0, and p0.1 is assigned to rx0. - the smbus is next in priority order, so p0.2 is assigned to sda, and p0.3 is assigned to scl. - uart1 is next in priority order, so p0.4 is assigned to tx1. because the external memory inter - face is selected on the lower ports, emifle = 1, which causes the crossbar to skip p0.6 (/rd) and p0.7 (/wr). because the external memory interface is configured in multi plexed mode, the cross - bar will also skip p0.5 (ale). rx1 is assigned to the next non-skipped pin, which in this case is p1.0. - /int0 is next in priority order, so it is assigned to p1.1. - p1mdin is set to 0xe3, which configures p1.2 , p1.3, and p1.4 as an alog inputs, causing the crossbar to skip these pins. - /int1 is next in priority order, so it is assigned to the next non-skipped pin, which is p1.5. - the external memory interface will drive ports 2 and 3 (denoted by red dots in figure 17.6 ) during the execution of an off- chip movx instruction. 5. we set the uart0 tx pin (tx0, p0.0), uart1 tx pin (tx1, p0.4), ale, /rd, /wr (p0.[7:3]) outputs to push-pull by setting p0mdout = 0xf1. 6. we configure the output modes of the emif ports (p2, p3) to push-pull by setting p2mdout = 0xff and p3mdout = 0xff. 7. we explicitly disable the output drivers on the 3 analog input pins by setting p1mdout = 0x00 (configure outputs to open-drain) and p1 = 0xff (a logic 1 selects the high-impedance state).
c8051f020/1/2/3 rev. 1.4 169 figure 17.6. crossbar example: (emifle = 1; emif in multiplexed mode; p1mdin = 0xe3; xbr0 = 0x05; xbr1 = 0x14; xbr2 = 0x46) pin i/o01234567012345670123456701234567 tx0 rx0 sck miso mosi nss sda scl tx1 rx1 cex0 cex1 cex2 cex3 cex4 eci eci0e: xbr0.6 cp0 cp0e: xbr0.7 cp1 cp1e: xbr1.0 t0 t0e: xbr1.1 /int0 int0e: xbr1.2 t1 t1e: xbr1.3 /int1 int1e: xbr1.4 t2 t2e: xbr1.5 t2ex t2exe: xbr1.6 t4 t4e: xbr2.3 t4ex t4exe: xbr2.4 /sysclk syscke: xbr1.7 cnvstr cnvste: xbr2.0 ale /rd /wr ain1.0/a8 ain1.1/a9 ain1.2/a10 ain1.3/a11 ain1.4/a12 ain1.5/a13 ain1.6/a14 ain1.7/a15 a8m/a0 a9m/a1 a10m/a2 a11m/a3 a12m/a4 a13m/a5 a14m/a6 a15m/a7 ad0/d0 ad1/d1 ad2/d2 ad3/d3 ad4/d4 ad5/d5 ad6/d6 ad7/d7 p0 p1 p2 p3 ain1 inputs/non-muxed addr h muxed addr h/non-muxed addr l muxed data/non-muxed data uart1en: pca0me: crossbar register bits xbr0.2 xbr0.1 xbr0.0 smb0en: xbr2.2 xbr0.[5:3] uart0en: spi0en:
c8051f020/1/2/3 170 rev. 1.4 figure 17.7. xbr0: port i/o crossbar register 0 bit7: cp0e: comparator 0 output enable bit. 0: cp0 unavailable at port pin. 1: cp0 routed to port pin. bit6: eci0e: pca0 external counter input enable bit. 0: pca0 external counter input unavailable at port pin. 1: pca0 external counter input (eci0) routed to port pin. bits5-3: pca0me: pca0 module i/o enable bits. 000: all pca0 i/o unavailable at port pins. 001: cex0 routed to port pin. 010: cex0, cex1 routed to 2 port pins. 011: cex0, cex1, and cex2 routed to 3 port pins. 100: cex0, cex1, cex2, and cex3 routed to 4 port pins. 101: cex0, cex1, cex2, cex3, and cex4 routed to 5 port pins. 110: reserved 111: reserved bit2: uart0en: uart0 i/o enable bit. 0: uart0 i/o unavailable at port pins. 1: uart0 tx routed to p0.0, and rx routed to p0.1. bit1: spi0en: spi0 bus i/o enable bit. 0: spi0 i/o unavaila ble at port pins. 1: spi0 sck, miso, mosi, and nss routed to 4 port pins. bit0: smb0en: smbus0 bus i/o enable bit. 0: smbus0 i/o unavailable at port pins. 1: smbus0 sda and scl routed to 2 port pins. r/w r/w r/w r/w r/w r/w r/w r/w reset value cp0e eci0e pca0me uart0en spi0en smb0en 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe1
c8051f020/1/2/3 rev. 1.4 171 figure 17.8. xbr1: port i/o crossbar register 1 bit7: syscke: /sysclk output enable bit. 0: /sysclk unavailable at port pin. 1: /sysclk routed to port pin. bit6: t2exe: t2ex input enable bit. 0: t2ex unavailable at port pin. 1: t2ex routed to port pin. bit5: t2e: t2 input enable bit. 0: t2 unavailable at port pin. 1: t2 routed to port pin. bit4: int1e: /int1 input enable bit. 0: /int1 unavailable at port pin. 1: /int1 routed to port pin. bit3: t1e: t1 input enable bit. 0: t1 unavailable at port pin. 1: t1 routed to port pin. bit2: int0e: /int0 input enable bit. 0: /int0 unavailable at port pin. 1: /int1 routed to port pin. bit1: t0e: t0 input enable bit. 0: t0 unavailable at port pin. 1: t0 routed to port pin. bit0: cp1e: cp1 output enable bit. 0: cp1 unavailable at port pin. 1: cp1 routed to port pin. r/w r/w r/w r/w r/w r/w r/w r/w reset value syscke t2exe t2e int1e t1e int0e t0e cp1e 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe2
c8051f020/1/2/3 172 rev. 1.4 figure 17.9. xbr2: port i/o crossbar register 2 bit7: weakpud: weak pull-up disable bit. 0: weak pull-ups globally enabled. 1: weak pull-ups globally disabled. bit6: xbare: crossbar enable bit. 0: crossbar disabled. all pins on ports 0, 1, 2, and 3, are forced to input mode. 1: crossbar enabled. bit5: unused. read = 0, write = don't care. bit4: t4exe: t4ex input enable bit. 0: t4ex unavailable at port pin. 1: t4ex routed to port pin. bit3: t4e: t4 input enable bit. 0: t4 unavailable at port pin. 1: t4 routed to port pin. bit2: uart1e: uart1 i/o enable bit. 0: uart1 i/o unavailable at port pins. 1: uart1 tx and rx routed to 2 port pins. bit1: emifle: external memory interface low-port enable bit. 0: p0.7, p0.6, and p0.5 functions are determ ined by the crossbar or the port latches. 1: if emi0cf.4 = ?0? (external memory interface is in multiplexed mode) p0.7 (/wr), p0.6 (/rd), and p0.5 (ale) ar e ?skipped? by the crossbar and their output states are determined by the port latc hes and the external memory interface. 1: if emi0cf.4 = ?1? (external memory interface is in non-multiplexed mode) p0.7 (/wr) and p0.6 (/rd) are ?skipped? by the crossbar and their output states are determined by the port latches and the external memory interface. bit0: cnvste: external convert start input enable bit. 0: cnvstr unavailable at port pin. 1: cnvstr routed to port pin. r/w r/w r/w r/w r/w r/w r/w r/w reset value weakpud xbare - t4exe t4e uart1e emifle cnvste 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe3
c8051f020/1/2/3 rev. 1.4 173 figure 17.10. p0: port0 data register bits7-0: p0.[7:0]: port0 output latch bits. (write - output appears on i/o pins pe r xbr0, xbr1, xbr2, and xbr3 registers) 0: logic low output. 1: logic high output (open if corresponding p0mdout.n bit = 0). (read - regardless of xbr0, xbr1, xbr2, and xbr3 register settings). 0: p0.n pin is logic low. 1: p0.n pin is logic high. note: p0.7 (/wr), p0.6 (/rd), and p0.5 (ale) can be driven by the external data memory interface. see section ?16. external data memory interface and on-chip xram? on page 145 for more information. see also figure 17.9 for information about configuring the crossbar for external memory accesses. r/w r/w r/w r/w r/w r/w r/w r/w reset value p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0x80 figure 17.11. p0mdout: port0 output mode register bits7-0: p0mdout.[7:0]: port0 output mode bits. 0: port pin output mode is configured as open-drain. 1: port pin output mode is configured as push-pull. note: sda, scl, and rx0 (when uart0 is in mode 0) and rx1 (when uart1 is in mode 0) are always configured as open-drain when they appear on port pins. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa4
c8051f020/1/2/3 174 rev. 1.4 figure 17.12. p1: port1 data register bits7-0: p1.[7:0]: port1 output latch bits. (write - output appears on i/o pins pe r xbr0, xbr1, xbr2, and xbr3 registers) 0: logic low output. 1: logic high output (open if corresponding p1mdout.n bit = 0). (read - regardless of xbr0, xbr1, xbr2, and xbr3 register settings). 0: p1.n pin is logic low. 1: p1.n pin is logic high. notes: 1. p1.[7:0] can be configured as inputs to adc1 as ain1.[7:0], in which case they are ?skipped? by the crossbar assignment process and th eir digital input paths are disabled, depending on p1mdin (see figure 17.13 ) . note that in analog mode, the output mode of the pin is determined by the port 1 latch and p1mdout (figure 17.14). see section ?7. adc1 (8-bit adc)? on page 75 for more informa- tion about adc1. 2. p1.[7:0] can be driven by the ex ternal data memory interface (as address[15:8] in non-multiplexed mode). see section ?16. external data memory interface and on-chip xram? on page 145 for more information about the external memory interface. r/w r/w r/w r/w r/w r/w r/w r/w reset value p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0x90 figure 17.13. p1mdin: port1 input mode register bits7-0: p1mdin.[7:0]: port 1 input mode bits. 0: port pin is configured in analog input mode. th e digital input path is disabled (a read from the port bit will always return ?0?). the weak pull-up on the pin is disabled. 1: port pin is configured in digital input mode. a read from the port bit will return the logic level at the pin. the state of the w eak pull-up is determined by the weakpud bit (xbr2.7, see figure 17.9). r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xbd
c8051f020/1/2/3 rev. 1.4 175 figure 17.14. p1mdout: port1 output mode register bits7-0: p1mdout.[7:0]: port1 output mode bits. 0: port pin output mode is configured as open-drain. 1: port pin output mode is configured as push-pull. note: sda, scl, and rx0 (when uart0 is in mode 0) and rx1 (when uart1 is in mode 0) are always configured as open-drain when they appear on port pins. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa5 figure 17.15. p2: port2 data register bits7-0: p2.[7:0]: port2 output latch bits. (write - output appears on i/o pins pe r xbr0, xbr1, xbr2, and xbr3 registers) 0: logic low output. 1: logic high output (open if corresponding p2mdout.n bit = 0). (read - regardless of xbr0, xbr1, xbr2, and xbr3 register settings). 0: p2.n pin is logic low. 1: p2.n pin is logic high. note: p2.[7:0] can be driven by the external data memory interface (as addre ss[15:8] in multiplexed mode, or as address[7:0] in non-multiplexed mode). see section ?16. external data mem- ory interface and on-chip xram? on page 145 for more information about the external memory interface. r/w r/w r/w r/w r/w r/w r/w r/w reset value p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xa0 figure 17.16. p2mdout: port2 output mode register bits7-0: p2mdout.[7:0]: port2 output mode bits. 0: port pin output mode is configured as open-drain. 1: port pin output mode is configured as push-pull. note: sda, scl, and rx0 (when uart0 is in mode 0) and rx1 (when uart1 is in mode 0) are always configured as open-drain when they appear on port pins. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa6
c8051f020/1/2/3 176 rev. 1.4 figure 17.17. p3: port3 data register bits7-0: p3.[7:0]: port3 output latch bits. (write - output appears on i/o pins pe r xbr0, xbr1, xbr2, and xbr3 registers) 0: logic low output. 1: logic high output (open if corresponding p3mdout.n bit = 0). (read - regardless of xbr0, xbr1, xbr2, and xbr3 register settings). 0: p3.n pin is logic low. 1: p3.n pin is logic high. note: p3.[7:0] can be driven by the external data me mory interface (as ad[7:0] in multiplexed mode, or as d[7:0] in non-multiplexed mode). see section ?16. external data memory inter- face and on-chip xram? on page 145 for more information about the external memory interface. r/w r/w r/w r/w r/w r/w r/w r/w reset value p3.7 p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xb0 figure 17.18. p3mdout: port3 output mode register bits7-0: p3mdout.[7:0]: port3 output mode bits. 0: port pin output mode is configured as open-drain. 1: port pin output mode is configured as push-pull. note: sda, scl, and rx0 (when uart0 is in mode 0) and rx1 (when uart1 is in mode 0) are always configured as open-drain when they appear on port pins. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa7
c8051f020/1/2/3 rev. 1.4 177 17.2. ports 4 through 7 (c8051f020/2 only) all port pins on ports 4 through 7 can be accessed as general-purpos e i/o (gpio) pins by reading and writing the associated port data registers (see figure 17.21 , figure 17.22 , figure 17.23 , and figure 17.24 ), a set of sfrs which are byte-addressable. a read of a port data register (or port bit) will always re turn the logic state present at the pin itself, regardless of whether the crossbar has allocated the pi n for peripheral use or not. an excep tion to this occurs during the execution of a read-modify-write instruction (anl, orl, xrl, cpl, inc, dec, djnz, jbc, clr, set, and the bitwise mov operation). during the read cycle of the read-modify-write instruction, it is the contents of the port data register, not the state of the port pins themselves, which is read. 17.2.1. configuring ports which are not pinned out although p4, p5, p6, and p7 are not brought out to pins on the c8051f021/3 devices, the port data registers are still present and can be used by software. becau se the digital input paths also remain active, it is recommended that these pins not be left in a ?floating? state in order to avoid unn ecessary power dissipation arising from the inputs floating to non-valid logic levels. this condition can be prevented by any of the following: 1. leave the weak pull-up devices enabled by setting weakpud (xbr2.7) to a logic 0. 2. configure the output modes of p4, p5, p6, and p7 to ?push-pull? by writing p74out = 0xff. 3. force the output states of p4, p5, p6, and p7 to logic 0 by writing zeros to the port data regis - ters: p4 = 0x00, p5 = 0x00, p6= 0x00, and p7 = 0x00. 17.2.2. configuring the output modes of the port pins the output mode of each port pin can be configured to be either open-drain or push-pull. in the push-pull configura - tion, a logic 0 in the associated bit in the port data register will cause the port pin to be driven to gnd, and a logic 1 will cause the port pin to be driven to vd d. in the open-drain configuration, a logic 0 in the associated bit in the figure 17.19. p3if: port3 interrupt flag register bit7: ie7: external interrupt 7 pending flag 0: no falling edge has been detected on p3.7 since this bit was last cleared. 1: this flag is set by hardware when a falling edge on p3.7 is detected. bit6: ie6: external interrupt 6 pending flag 0: no falling edge has been detected on p3.6 since this bit was last cleared. 1: this flag is set by hardware when a falling edge on p3.6 is detected. bits5-4: unused. read = 00b, write = don?t care. bit3: ie7cf: external interrupt 7 edge configuration 0: external interrupt 7 triggered by a falling edge on the ie7 input. 1: external interrupt 7 triggered by a rising edge on the ie7 input. bit2: ie6cf: external interrupt 6 edge configuration 0: external interrupt 6 triggered by a falling edge on the ie6 input. 1: external interrupt 6 triggered by a rising edge on the ie6 input. bits1-0: unused. read = 00b, write = don?t care. r/w r/w r r r/w r/w r/w r/w reset value ie7 ie6 - - ie7cf ie6cf - - 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xad
c8051f020/1/2/3 178 rev. 1.4 port data register will cause the port pin to be driven to gnd, and a logic 1 will cause the port pin to assume a high- impedance state. the open-drain config uration is useful to prevent contenti on between devices in systems where the port pin participates in a shared interconnection in which multiple outputs are connected to the same physical wire. the output modes of the port pins on ports 4 through 7 are determined by the bits in the p74out register (see figure 17.20 ). each bit in p74out controls the output mode of a 4-bit bank of port pins on ports 4, 5, 6, and 7. a logic 1 in p74out.7 will configure the output modes of 4 most-significant bits of port 7, p7.[7:4], to push-pull; a logic 0 in p74out.7 will configure the output modes of p7.[7:4] to open-drain. 17.2.3. configuring port pins as digital inputs a port pin is configured as a digital input by settin g its output mode to ?open-drain? and writing a logic 1 to the associated bit in the port data register. for example, p7.7 is configured as a digital input by setting p74out.7 to a logic 0 and p7.7 to a logic 1. 17.2.4. weak pull-ups by default, each port pin has an internal weak pull-up device enabled which provides a resistive connection (about 100 k ? ) between the pin and vdd. the weak pull-up devices can be globally disabled by writing a logic 1 to the weak pull-up disable bit, (weakpud, x br2.7). the weak pull-up is automati cally deactivated on any pin that is driving a logic 0; that is, an output pin will not contend with its own pull-up device. 17.2.5. external memory interface if the external memory interface (emif) is enable d on the high ports (ports 4 through 7), emifle (xbr2.1) should be set to a logic 0. if the external memory interface is enabled on the high ports and an off-chip movx operation occurs, the external memory interface will control the output states of the affected port pins during the execution phase of the movx instruction, regardless of the settings of the port data regi sters. the output configuration of the port pins is not affected by the emif operation, except th at read operations will explicitly disable the output drivers on the data bus during the movx execution. see section ?16. external data memory interface and on-chip xram? on page 145 for more information about the external memory interface.
c8051f020/1/2/3 rev. 1.4 179 figure 17.20. p74out: ports 7 - 4 output mode register bit7: p7h: port7 output mode high nibble bit. 0: p7.[7:4] configured as open-drain. 1: p7.[7:4] configured as push-pull. bit6: p7l: port7 output mode low nibble bit. 0: p7.[3:0] configured as open-drain. 1: p7.[3:0] configured as push-pull. bit5: p6h: port6 output mode high nibble bit. 0: p6.[7:4] configured as open-drain. 1: p6.[7:4] configured as push-pull. bit4: p6l: port6 output mode low nibble bit. 0: p6.[3:0] configured as open-drain. 1: p6.[3:0] configured as push-pull. bit3: p5h: port5 output mode high nibble bit. 0: p5.[7:4] configured as open-drain. 1: p5.[7:4] configured as push-pull. bit2: p5l: port5 output mode low nibble bit. 0: p5.[3:0] configured as open-drain. 1: p5.[3:0] configured as push-pull. bit1: p4h: port4 output mode high nibble bit. 0: p4.[7:4] configured as open-drain. 1: p4.[7:4] configured as push-pull. bit0: p4l: port4 output mode low nibble bit. 0: p4.[3:0] configured as open-drain. 1: p4.[3:0] configured as push-pull. r/w r/w r/w r/w r/w r/w r/w r/w reset value p7h p7l p6h p6l p5h p5l p4h p4l 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb5
c8051f020/1/2/3 180 rev. 1.4 figure 17.21. p4: port4 data register bits7-0: p4.[7:0]: port4 output latch bits. write - output appears on i/o pins. 0: logic low output. 1: logic high output (open-drain if corresponding p74out bit = 0). see figure 17.20. read - returns states of i/o pins. 0: p4.n pin is logic low. 1: p4.n pin is logic high. note: p4.7 (/wr), p4.6 (/rd), and p4.5 (ale) can be driven by the external data memory interface. see section ?16. external data memory interface and on-chip xram? on page 145 for more information. r/w r/w r/w r/w r/w r/w r/w r/w reset value p4.7 p4.6 p4.5 p4.4 p4.3 p4.2 p4.1 p4.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x84 figure 17.22. p5: port5 data register bits7-0: p5.[7:0]: port5 output latch bits. write - output appears on i/o pins. 0: logic low output. 1: logic high output (open-drain if corresponding p74out bit = 0). see figure 17.20. read - returns states of i/o pins. 0: p5.n pin is logic low. 1: p5.n pin is logic high. note: p5.[7:0] can be driven by the external data me mory interface (as address[ 15:8] in non- multiplexed mode). see section ?16. external data memory interface and on-chip xram? on page 145 for more information about the external memory interface. r/w r/w r/w r/w r/w r/w r/w r/w reset value p5.7 p5.6 p5.5 p5.4 p5.3 p5.2 p5.1 p5.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x85
c8051f020/1/2/3 rev. 1.4 181 figure 17.23. p6: port6 data register bits7-0: p6.[7:0]: port6 output latch bits. write - output appears on i/o pins. 0: logic low output. 1: logic high output (open-drain if corresponding p74out bit = 0). see figure 17.20. read - returns states of i/o pins. 0: p6.n pin is logic low. 1: p6.n pin is logic high. note: p6.[7:0] can be driven by the external data memory interface (as addre ss[15:8] in multiplexed mode, or as address[7:0] in non-multiplexed mode). see section ?16. external data mem- ory interface and on-chip xram? on page 145 for more information about the external memory interface. r/w r/w r/w r/w r/w r/w r/w r/w reset value p6.7 p6.6 p6.5 p6.4 p6.3 p6.2 p6.1 p6.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x86 figure 17.24. p7: port7 data register bits7-0: p7.[7:0]: port7 output latch bits. write - output appears on i/o pins. 0: logic low output. 1: logic high output (open-drain if corresponding p74out bit = 0). see figure 17.20. read - returns states of i/o pins. 0: p7.n pin is logic low. 1: p7.n pin is logic high. note: p7.[7:0] can be driven by the external data me mory interface (as ad[7:0] in multiplexed mode, or as d[7:0] in non-multiplexed mode). see section ?16. external data memory inter- face and on-chip xram? on page 145 for more information about the external memory interface. r/w r/w r/w r/w r/w r/w r/w r/w reset value p7.7 p7.6 p7.5 p7.4 p7.3 p7.2 p7.1 p7.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x96
c8051f020/1/2/3 182 rev. 1.4 notes
c8051f020/1/2/3 rev. 1.4 183 18. system management bus / i 2 c bus (smbus0) the smbus0 i/o interface is a two-wire , bi-directional serial bus. smbus0 is compliant with the system manage - ment bus specification, version 1. 1, and compatible with the i 2 c serial bus. reads and writes to the interface by the system controller are byte or iented with the smbus0 inte rface autonomously controlling the serial transfer of the data. data can be transferred at up to 1/8th of the system clock if desired (this can be faster than allowed by the smbus specification, depending on the system clock used). a method of extending the clock-low duration is avail - able to accommodate devices with diff erent speed capabilitie s on the same bus. smbus0 may operate as a master and/or slave, and may function on a bus with multiple masters. smbus0 provides control of sda (serial data), scl (ser ial clock) generation and synchronizatio n, arbitration logic, and start/stop control and generation. smbus0 is controlled by sfrs as described in section 18.4 on page 189 . figure 18.1. smbus0 block diagram sfr bus data path control sfr bus write to smb0dat smbus control logic read smb0dat smb0adr s l v 6 g c s l v 5 s l v 4 s l v 3 s l v 2 s l v 1 s l v 0 c r o s s b a r clock divide logic sysclk smb0cr c r 7 c r 6 c r 5 c r 4 c r 3 c r 2 c r 1 c r 0 scl filter n sda control 0000000b 7 msbs 8 a b a=b 8 0 1 2 3 4 5 6 7 smb0dat 8 smb0cn s t a s i a a f t e t o e e n s m b b u s y s t o smb0sta s t a 4 s t a 3 s t a 2 s t a 1 s t a 0 scl control status generation arbitration scl synchronization scl generation (master mode) irq generation s t a 5 s t a 6 s t a 7 a b a=b smbus irq interrupt request port i/o 1 0 sda filter n 7
c8051f020/1/2/3 184 rev. 1.4 figure 18.2 shows a typical smbus configurat ion. the smbus0 interface will wo rk at any voltage between 3.0 v and 5.0 v and different devices on the bus may operate at differ ent voltage levels. the bi-directional scl (serial clock) and sda (serial data) lines must be connected to a positiv e power supply voltage through a pull-up resistor or similar circuit. every device connected to the bus must have an open-drain or open-collector output for both the scl and sda lines, so that both are pulled high when the bus is free. the maximum number of devices on the bus is limited only by the requirement that th e rise and fall times on the bus will not exceed 300 ns and 1000 ns, respectively. 18.1. supporting documents it is assumed the reader is familiar with or has access to the following supporting documents: 1. the i 2 c-bus and how to use it (including specifications), philips semiconductor. 2. the i 2 c-bus specification -- version 2.0, philips semiconductor. 3. system management bus specification -- version 1.1, sbs implementers forum. figure 18.2. typical smbus configuration vdd = 5v master device slave device 1 slave device 2 vdd = 3v vdd = 5v vdd = 3v sda scl
c8051f020/1/2/3 rev. 1.4 185 18.2. smbus protocol two types of data transfers are possib le: data transfers from a master tran smitter to an addressed slave receiver (write), and data transfers from an addressed slave transmitter to a master receiver (read). the master device ini - tiates both types of data transfers and provides the serial clock pulses on scl. note: multiple master devices on the same bus are supported. if two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme is employed with a single master always winning the arbitration. note that it is not necessary to specify one device as the master in a system; any device who transmits a start and a slave address becomes the master for that transfer. a typical smbus transaction consists of a start cond ition followed by an address byte (bits7-1: 7-bit slave address; bit0: r/w direction b it), one or more bytes of data, and a stop condition. each byte that is received (by a master or slave) must be acknowledged (a ck) with a low sda during a high scl (see figure 18.3 ). if the receiving device does not ack, the transmitting device will read a ?not acknowledge? (nack), which is a high sda during a high scl. the direction bit (r/w) occupies the least- significant bit position of the address. the direction bit is set to logic 1 to indicate a "read" operation and cleared to logic 0 to indicate a "write" operation. all transactions are initiated by a master , with one or more addressed slave devi ces as the target. the master gener - ates the start condition and then transm its the slave address and direction bit. if the transaction is a write opera - tion from the master to the slave, the ma ster transmits the data a byte at a time waiting for an ac k from the slave at the end of each byte. for read operations , the slave transmits the data waiting for an ack from the master at the end of each byte. at the end of the data transfer, the mast er generates a stop condition to terminate the transaction and free the bus. figure 18.3 illustrates a typical smbus transaction. 18.2.1. arbitration a master may start a transfer only if the bus is free. th e bus is free after a stop condition or after the scl and sda lines remain high for a specified time (see section 18.2.4 ). in the event that two or mo re devices attempt to begin a transfer at the same time, an arbitrat ion scheme is employed to force one master to give up the bus. the master devices continue transmitting until one attempts a high while the other transmits a low. since the bus is open- drain, the bus will be pulled low. the master attempting th e high will detect a low sd a and give up the bus. the winning master continues its transmissi on without interruption; the losing master becomes a slave and receives the rest of the transfer. this arbitration scheme is non-des tructive: one device always wins, and no data is lost. 18.2.2. clock low extension smbus provides a clock synchroni zation mechanism, similar to i 2 c, which allows devices with different speed capa - bilities to coexist on the bus. a clock-low extension is used during a transfer in order to allow slower slave devices to communicate with faster masters. the slave may temporarily hold the scl line low to extend the clock low period, effectively decreasing the serial clock frequency. sla6 sda sla5-0 r/w d7 d6-0 scl slave address + r/w data byte start ack nack stop figure 18.3. smbus transaction
c8051f020/1/2/3 186 rev. 1.4 18.2.3. scl low timeout if the scl line is held low by a slave device on the bus, no further communication is possible. furthermore, the mas - ter cannot force the scl line high to co rrect the error condition. to solve this problem, the smbus protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than 25 ms as a ?timeout? condi - tion. devices that have detected the timeout condition must reset the communication no later than 10 ms after detect - ing the timeout condition. 18.2.4. scl high (smbus free) timeout the smbus specification stipulates that if the scl and sda lines remain high for more that 50 s, the bus is desig - nated as free. if an smbus device is waiting to generate a master start, the start will be generated following a bus free timeout.
c8051f020/1/2/3 rev. 1.4 187 18.3. smbus transfer modes the smbus0 interface may be configured to operate as a master and/or a slave. at any particular time, the interface will be operating in one of the followi ng modes: master transmitter, master receiver, slave transmitter, or slave receiver. see table 18.1 for transfer mode status decoding using the smb0sta status register. the following mode descriptions illustrate an interrupt-driven smbus0 appli cation; smbus0 may alternatively be operated in polled mode. 18.3.1. master transmitter mode serial data is transmitted on sda whil e the serial clock is output on scl. smbus0 generates a start condition and then transmits the first byte cont aining the address of the target slave device and the data direction bit. in this case the data direction bit (r/w) will be lo gic 0 to indicate a "write" operation. the smbus0 interface transmits one or more bytes of serial data, waiting for an acknowledge (ack) from the slave afte r each byte. to indicate the end of the serial transfer, smbus0 generates a stop condition. 18.3.2. master receiver mode serial data is received on sda while the serial clock is output on scl. the smbus0 interface generates a start followed by the first data byte containing the address of the ta rget slave and the data directio n bit. in this case the data direction bit (r/w) will be lo gic 1 to indicate a "read" operation. the sm bus0 interface receives serial data from the slave and generates the clock on scl. after each byte is received, sm bus0 generates an ack or nack depend - ing on the state of the aa bit in register smb0cn. smbus0 generates a stop condition to indicate the end of the serial transfer. a a a s w p data byte data byte sla s = start p = stop a = ack w = write sla = slave address received by smbus interface transmitted by smbus interface interrupt interrupt interrupt interrupt figure 18.4. typical master transmitter sequence data byte data byte a n a s r p sla s = start p = stop a = ack n = nack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupt interrupt interrupt interrupt figure 18.5. typical master receiver sequence
c8051f020/1/2/3 188 rev. 1.4 18.3.3. slave transmitter mode serial data is transmitted on sda while the serial cloc k is received on scl. the smbu s0 interface receives a start followed by data byte containi ng the slave address and direction bit. if the received slave address matches the address held in register smb0adr, the smbus0 interface generates an ack. smbus0 will also ack if the general call address (0x00) is received and the general call address enab le bit (smb0adr.0) is set to logic 1. in this case the data direction bit (r/w) will be logic 1 to indicate a "read" operation. the smbus0 interface receives the clock on scl and transmits one or more bytes of serial data, waiting for an ack fr om the master after each byte. smbus0 exits slave mode after receiving a stop condition from the master. 18.3.4. slave receiver mode serial data is received on sda while the serial clock is received on scl. the smbus0 interface receives a start followed by data byte containi ng the slave address and direction bit. if the received slave address matches the address held in register smb0adr, the interface generates an ack. smbus0 w ill also ack if the general call address (0x00) is received and the general call address enable bit (smb 0adr.0) is set to logic 1. in this case the data direc - tion bit (r/w) will be logic 0 to indicate a "write" operat ion. the smbus0 interface receives one or more bytes of serial data; after each byte is receive d, the interface transmits an ack or nac k depending on the state of the aa bit in smb0cn. smbus0 exits slave receiver mode af ter receiving a stop condition from the master. p r sla s data byte data byte a n a s = start p = stop n = nack w = write sla = slave address received by smbus interface transmitted by smbus interface interrupt interrupt interrupt interrupt figure 18.6. typical slave transmitter sequence p w sla s data byte data byte a a a s = start p = stop a = ack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupt interrupt interrupt interrupt figure 18.7. typical slave receiver sequence
c8051f020/1/2/3 rev. 1.4 189 18.4. smbus special function registers the smbus0 serial interface is accessed and controlled through five sfrs: smb0cn control register, smb0cr clock rate register, smb0adr address register, smb0da t data register and smb0sta status register. the five special function registers related to the operation of the smbus0 interf ace are described in the following sec - tions. 18.4.1. control register the smbus0 control register smb0cn is used to configure and control the smbu s0 interface. all of the bits in the register can be read or written by soft ware. two of the control bits are also affected by the smbus0 hardware. the serial interrupt flag (si, smb0cn.3) is set to logic 1 by the hardware when a valid seri al interrupt condition occurs. it can only be cleared by software. the stop flag (sto, smb0cn.4) is cleared to logic 0 by hardware when a stop condition is detected on the bus. setting the ensms flag to l ogic 1 enables the smbus0 inte rface. clearing the ensmb flag to logic 0 disables the smbus0 interface and removes it from th e bus. momentarily clearing the ensmb flag and then resetting it to logic 1 will reset smbus0 communication. however, ensmb should not be used to temporarily remove a device from the bus since the bus state information will be lost. instead, the assert acknowledge (aa) flag should be used to tempo - rarily remove the device from the bus (see description of aa flag below). setting the start flag (sta, smb0cn.5) to logic 1 will put sm bus0 in a master mode. if the bus is free, smbus0 will generate a start condition. if the bus is not free, smbus0 waits for a stop condition to free the bus and then gen - erates a start condition after a 5 s delay per the smb0cr value (in acco rdance with the smbus protocol, the smbus0 interface also considers the bus free if the bus is idle for 50 s and no stop condition was recognized). if sta is set to logic 1 while smbus0 is in master mode an d one or more bytes have b een transferred, a repeated start condition will be generated. to ensure proper operation, the sto bit should be explicitly cleared to ?0? before setting the sta bit to ?1?. when the stop flag (sto, smb0cn.4) is set to logic 1 while the smbus0 inte rface is in master mode, the interface generates a stop condition. in a slave mode, the sto flag may be used to recover from an error condition. in this case, a stop condition is not generated on the bus, but th e smbus hardware behaves as if a stop condition has been received and enters the "not addressed" slave receiver mode. note that this simulated stop will not cause the bus to appear free to smbus0. the bus will remain occupied until a stop appears on the bus or a bus free timeout occurs. hardware automatically clears the st o flag to logic 0 when a stop condition is detected on the bus. the serial interrupt flag (s i, smb0cn.3) is set to logic 1 by hardware when the smbus0 interface enters one of 27 possible states. if interrupts ar e enabled for the smbus0 interface, an interr upt request is generated when the si flag is set. the si flag must be cleared by software. important note: if si is set to logic 1 while the scl line is lo w, the clock-low period of the serial clock will be stretched and the serial transfer is susp ended until si is cleared to logic 0. a high level on scl is not affected by the setting of the si flag. the assert acknowledge flag (aa, smb0cn.2) is used to set the level of the sda line during the acknowledge clock cycle on the scl line. setting the aa flag to logic 1 will cause an ack (low level on sda) to be sent during the acknowledge cycle if the device has been addressed. se tting the aa flag to logic 0 will cause a nack (high level on sda) to be sent during acknowledge cycle. after the transmission of a byte in slave mode, the slave can be tempo - rarily removed from the bus by clearing the aa flag. the slave's own address and general call address will be ignored. to resume operation on the bus, the aa flag must be reset to logic 1 to allow the slave's address to be recog - nized.
c8051f020/1/2/3 190 rev. 1.4 setting the smbus0 free timer enable bit (fte, smb0cn.1) to logic 1 enables the timer in smb0cr. when scl goes high, the timer in smb0cr counts up. a timer overflow i ndicates a free bus timeout: if smbus0 is waiting to generate a start, it will do so after this timeout. the bus free period should be less than 50 s (see figure 18.9 , smbus0 clock rate register). when the toe bit in smb0cn is set to logic 1, timer 3 is used to detect scl low timeouts. if timer 3 is enabled (see section ?22.2. timer 3? on page 240 ), timer 3 is forced to reload when scl is high, and for ced to count when scl is low. with timer 3 enabled and configured to overflow after 25 ms (and toe set), a timer 3 overflow indi - cates a scl low timeout; the timer 3 interrupt service rout ine can then be used to reset smbus0 communication in the event of an scl low timeout.
c8051f020/1/2/3 rev. 1.4 191 figure 18.8. smb0cn: smbus0 control register bit7: busy: busy status flag. 0: smbus0 is free 1: smbus0 is busy bit6: ensmb: smbus enable. this bit enables/disables the smbus serial interface. 0: smbus0 disabled. 1: smbus0 enabled. bit5: sta: smbus start flag. 0: no start condition is transmitted. 1: when operating as a master, a start condition is transmitted if the bus is free. (if the bus is not free, the start is transmitted afte r a stop is received.) if sta is set after one or more bytes have been transmitted or received and before a stop is received, a repeated start condition is transmit- ted. to ensure proper operation, the sto bit should be explicitly cleared to ?0? before setting the sta bit to ?1?. bit4: sto: smbus stop flag. 0: no stop condition is transmitted. 1: setting sto to logic 1 causes a stop condition to be transmitted. when a stop condition is received, hardware clears sto to logic 0. if both sta and sto are set, a st op condition is transmit- ted followed by a start condition. in slave mode, setting the sto flag causes smbus to behave as if a stop condition was received. bit3: si: smbus serial interrupt flag. this bit is set by hardware when one of 27 possible smbus0 states is entered. (status code 0xf8 does not cause si to be set.) when the si interrupt is enabled, setting this bit causes the cpu to vector to the smbus interrupt service routine. this bit is not automatically cleared by hardware and must be cleared by software. bit2: aa: smbus assert acknowledge flag. this bit defines the type of acknowledge returned during the acknowledge cycle on the scl line. 0: a "not acknowledge" (high level on sda) is returned during the acknowledge cycle. 1: an "acknowledge" (low level on sda) is returned during the acknowledge cycle. bit1: fte: smbus free timer enable bit 0: no timeout when scl is high 1: timeout when scl high time exceeds limit specified by the smb0cr value. bit0: toe: smbus timeout enable bit 0: no timeout when scl is low. r r/w r/w r/w r/w r/w r/w r/w reset value busy ensmb sta sto si aa fte toe 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xc0
c8051f020/1/2/3 192 rev. 1.4 18.4.2. clock rate register figure 18.9. smb0cr: smbus0 clock rate register bits7-0: smb0cr.[7:0]: smbus0 clock rate preset the smb0cr clock rate register controls the frequency of the serial clock scl in master mode. the 8-bit word stored in the smb0cr register preloads a dedicated 8-bit timer. the timer counts up, and when it rolls over to 0x00, the scl logic state toggles. the smb0cr setting should be bounded by the following equation , where smb0cr is the unsigned 8-bit value in register smb0cr, and sysclk is the system clock frequency in hz: the resulting scl signal high and low times are given by the following equations: using the same value of smb0cr from above, the bus free timeout period is given in the following equation: r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xcf smb 0 cr 288 ( ( 0.85 ? sysclk ) 1.125 ) ? ? < t low 256 smb 0 cr ? () sysclk ? = t high 258 smb 0 cr ? () sysclk ? 625 ns + ? t bft 10 256 smb 0 cr ? () 1 + sysclk ----------------- ------------------ ----------------- - ?
c8051f020/1/2/3 rev. 1.4 193 18.4.3. data register the smbus0 data register smb0dat holds a byte of serial da ta to be transmitted or one that has just been received. software can read or write to this regist er while the si flag is set to logic 1; software should not attempt to access the smb0dat register when the smbus is enabled and the si flag is cleared to logic 0 since the hardware may be in the process of shifting a byte of da ta in or out of the register. data in smb0dat is always shifted out msb first. after a byte has been received, the first bit of received data is located at the msb of smb0dat. while data is being shifte d out, data on the bus is simultaneously being shifted in. therefore, smb0dat always contains the la st data byte present on the bus. in th e event of lost arb itration, the transi - tion from master transmitter to slave receiver is made with the correct data in smb0dat. 18.4.4. address register the smb0adr address register holds th e slave address for the smbus0 interf ace. in slave mode, the seven most- significant bits hold the 7-bit slave address. the least significant bit (bit0) is used to enable the recognition of the general call address (0x00). if bit0 is se t to logic 1, the general call address will be recognized. otherwise, the general call address is ignored. the contents of this register are ignored when sm bus0 is operating in master mode. figure 18.10. smb0dat: smbus0 data register bits7-0: smb0dat: smbus0 data. the smb0dat register contains a byte of data to be transmitted on the smbus0 serial interface or a byte that has just been received on the smbus0 seri al interface. the cpu can read from or write to this register whenever the si serial interrupt flag (smb0cn.3) is set to logic 1. when the si flag is not set, the system may be in the process of shifting data in/out and the cpu should not attempt to access this register. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc2 figure 18.11. smb0adr: smbus0 address register bits7-1: slv6-slv0: smbus0 slave address. these bits are loaded with the 7- bit slave address to which smbus0 will respond when operating as a slave transmitter or slave receiver. slv6 is the most significant bit of the address and corresponds to the first bit of the address byte received. bit0: gc: general call address enable. this bit is used to enable general call address (0x00) recognition. 0: general call address is ignored. 1: general call address is recognized. r/w r/w r/w r/w r/w r/w r/w r/w reset value slv6 slv5 slv4 slv3 slv2 slv1 slv0 gc 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc3
c8051f020/1/2/3 194 rev. 1.4 18.4.5. status register the smb0sta status register holds an 8-bit status code indicating the current state of the smbus0 interface. there are 28 possible smbus0 states, each with a corresponding unique stat us code. the five most significant bits of the status code vary while the three least-si gnificant bits of a valid stat us code are fixed at zero wh en si = ?1?. therefore, all possible status codes are multiples of eight. this facilitates the us e of status codes in software as an index used to branch to appropriate service routines (a llowing 8 bytes of code to service the state or jump to a more extensive ser - vice routine). for the purposes of user software, the cont ents of the smb0sta register is only defined when the si flag is logic 1. software should never write to the smb0sta register; doing so will yield indeterminate results. the 28 smbus0 states, along with their corresponding status codes, are given in table 1.1. figure 18.12. smb0sta: smbus0 status register bits7-3: sta7-sta3: smbus0 status code. these bits contain the smbus0 status code. there ar e 28 possible status code s; each status code cor- responds to a single smbus state. a valid status code is present in smb0sta when the si flag (smb0cn.3) is set to logic 1. the content of smb0sta is not defined when the si flag is logic 0. writing to the smb0sta register at any time will yield indeterminate results. bits2-0: sta2-sta0: the three least significant bits of smb0sta are always read as logic 0 when the si flag is logic 1. r/w r/w r/w r/w r/w r/w r/w r/w reset value sta7 sta6 sta5 sta4 sta3 sta2 sta1 sta0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc1
c8051f020/1/2/3 rev. 1.4 195 table 18.1. smb0sta status codes and states mode status code smbus state typical action mt/ mr 0x08 start condition transmitted. load smb0dat with slave address + r/w. clear sta. 0x10 repeated start condition transmitted. load smb0dat with slave address + r/w. clear sta. master transmitter 0x18 slave address + w transmitted. ack received. load smb0dat with data to be transmit - ted. 0x20 slave address + w transmitted. nack received. acknowledge poll to retry. set sto + sta. 0x28 data byte transmitt ed. ack received. 1) load smb0dat with next byte, or 2) set sto, or 3) clear sto then set sta for repeated start. 0x30 data byte transmitted. nack received. 1) retry transfer or 2) set sto. 0x38 arbitration lost. save current data. master receiver 0x40 slave address + r transmitted. ack received. if only receiving one byte, clear aa (send nack after received byte). wait for received data. 0x48 slave address + r transmitted. nack received. acknowledge poll to retry. set sto + sta. 0x50 data byte received. ack transmitted. read smb0dat. wait for next byte. if next byte is last byte, clear aa. 0x58 data byte received. nack transmitted. set sto.
c8051f020/1/2/3 196 rev. 1.4 slave receiver 0x60 own slave address + w received. ack trans - mitted. wait for data. 0x68 arbitration lost in sending sla + r/w as mas - ter. own address + w received. ack transmit - ted. save current data for retry when bus is free. wait for data. 0x70 general call address received. ack transmit - ted. wait for data. 0x78 arbitration lost in sending sla + r/w as mas - ter. general call address received. ack trans - mitted. save current data for retry when bus is free. 0x80 data byte received. ack transmitted. read smb0dat. wait for next byte or stop. 0x88 data byte received. nack transmitted. set sto to reset smbus. 0x90 data byte received after general call address. ack transmitted. read smb0dat. wait for next byte or stop. 0x98 data byte received after general call address. nack transmitted. set sto to reset smbus. 0xa0 stop or repeated start received. no action necessary. slave transmitter 0xa8 own address + r received. ack transmitted. load smb0dat with data to transmit. 0xb0 arbitration lost in transmitting sla + r/w as master. own address + r received. ack transmitted. save current data for retry when bus is free. load smb0dat with data to trans - mit. 0xb8 data byte transmitt ed. ack received. load smb0dat with data to transmit. 0xc0 data byte transmitted. nack received. wait for stop. 0xc8 last data byte transmitted (aa=0). ack received. set sto to reset smbus. slave 0xd0 scl clock high timer per smb0cr timed out set sto to reset smbus. all 0x00 bus error (illegal start or stop) set sto to reset smbus. 0xf8 idle state does not set si. table 18.1. smb0sta status codes and states mode status code smbus state typical action
c8051f020/1/2/3 rev. 1.4 197 19. serial peripheral interface bus (spi0) the serial peripheral interface (spi0) provides access to a four-w ire, full-duplex, serial bus. spi0 may operate as a master or a slave, and supports the connection of multiple slaves and masters on the same bus. a slave-select input (nss) is included in the spi0 interface to select spi0 as a slave; additi onal general purpose port i/o can be used as slave-select outputs when spi0 is ope rating as a master. collision detection is provided when tw o or more masters attempt a data transfer at the same time. when the spi is co nfigured as a master, the maxi mum data transfer rate (bits/ sec) is one-half the system clock frequency. when the spi is configured as a slave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the system clock frequency, provided that th e master issues sck, nss, and the serial input data synchronously with the system clock. if the master issues sc k, nss, and the serial input data asyn chronously, the maximum data transfer rate (bits/sec) must be less that 1/10 the system clock frequency. in the sp ecial case where the master only wants to transmit data to the slave and does not need to receive data from the slave (i .e. half-duplex operation), the spi slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. this is provided that the master issues sck, nss, and the serial in put data synchronously with the system clock. figure 19.1. spi block diagram sfr bus clock divide logic data path control sfr bus write to spi0dat receive data register spi0dat 0 1 2 3 4 5 6 7 shift register spi control logic bit count logic spi0ckr s c r 7 s c r 6 s c r 5 s c r 4 s c r 3 s c r 2 s c r 1 s c r 0 spi0cfg c k p h a c k p o l b c 2 b c 1 b c 0 f r s 2 f r s 1 f r s 0 spi0cn m o d f t x b s y s l v s e l m s t e n s p i e n w c o l s p i f r x o v r n pin control interface spi clock (master mode) pin control logic c r o s s b a r port i/o read spi0dat spi irq sysclk tx data rx data sck mosi miso nss
c8051f020/1/2/3 198 rev. 1.4 19.1. signal descriptions the four signals used by spi0 (mosi, miso, sck, nss) are described below. 19.1.1. master out, slave in (mosi) the master-out, slave-in (mosi) signal is an output from a master device and an input to slave devices. it is used to serially transfer data from the master to the slave. this signal is an output when spi0 is operating as a master, and an input when spi0 is operating as a slave. data is transferred most-significant bit first. 19.1.2. master in, slave out (miso) the master-in, slave-out (miso) signal is an output from a sl ave device and an input to th e master device. it is used to serially transfer data from the slave to the master. this signal is an input wh en spi0 is operating as a master, and an output when spi0 is operating as a slav e. data is transferred most-significant bit first. a spi slave places the miso pin in a high-impedance state wh en the slave is not selected. 19.1.3. serial clock (sck) the serial clock (sck) signal is an output from the master de vice and an input to slave devices. it is used to synchro - nize the transfer of data between the master and slave on the mosi and miso lines. spi0 generates this signal when operating as a master. 19.1.4. slave select (nss) the slave select (nss) signal is an input used to select spi0 as a slave, or to disable spi0 as a master. note that the nss signal is always an input to spi0; with spi0 operating as a master, slave select signals must be output via general purpose port i/o pins. see figure 19.2 for a typical configuration; see section ? 17.1. ports 0 through 3 and the pri - ority crossbar decoder ? on page 163 for general purpose port configuration. the nss signal must be low to initiate a transfer with sp i0 as a slave; spi0 will ex it slave mode when nss is released high. note that received data is not latched into the receive buffer un til nss is high. for multiple-byte trans - fers, nss must be released high for at least 4 system clocks following each byte that is received by the spi0 slave. figure 19.2. typical spi interconnection slave device slave device master device mosi slave device nss nss miso sck nss vdd gpio miso mosi sck
c8051f020/1/2/3 rev. 1.4 199 19.2. spi0 operation only a spi master device can initiate a data transfer. spi0 is placed in master mode by se tting the master enable flag (msten, spi0cn.1). writing a byte of data to the spi0 data register (spi0dat) when in master mode starts a data transfer. the spi0 master immediately sh ifts out the data serially on the mosi line while providing the serial clock on sck. the spif (spi0cn.7) flag is set to logic 1 at the end of the transfer. if interrupts are enabled, an interrupt request is generated when the spif flag is set. the spi0 mast er can be configured to shift in/out from one to eight bits in a transfer operation in order to accommodate slave devices with different word lengths. the spifrs bits in the sp0i configuration register (spi0cfg.[2:0] ) are used to select the number of bi ts to shift in/out in a transfer opera - tion. while the spi0 master transfers data to a slave on the mosi line, the addr essed spi slave device simultaneously transfers the contents of its shift regist er to the spi master on the miso line in a full-duplex operation. the data byte received from the slave replaces the data in the master's data register. therefor e, the spif flag serves as both a trans - mit-complete and receive-d ata-ready flag. the data transfer in both directions is synchronized with the serial clock generated by the master. figure 19.3 illustrates the full-duplex operation of an spi master and an addressed slave. when spi0 is enabled and not configured as a master, it will operate as an spi slave. another spi device acting as a master will initiate a transfer by driving the nss input signal low. the master then shifts data out of the shift register on the mosi pin using the its serial clock. the spif flag is set to logic 1 when the nss signal goes high, indicating the end of a data transfer. note that following a rising edge on nss, the recei ve buffer will always contain the last 8 bits of data in the slave shift register. the slave can load its shift register for th e next data transfer by writing to the spi0 data register. the slave must make the write to the da ta register at least one spi serial clock cycle before the master starts the next transmission. othe rwise, the byte of data already in the sl ave's shift register will be transferred. note that the nss signal must be driven low at least 2 system clocks before th e first active edge of sck for each byte transfer. the spi0 data register is double buffered on reads, but not on writes. if a write to spi0da t is attempted during a data transfer, the wcol flag (spi0cn.6) will be set to logic 1 a nd the write will be ignored. th e current data transfer will continue uninterrupted. a read of the sp i0 data register by the system controlle r actually reads the receive buffer. the receive overrun flag (rxovrn in regist er spi0cn) is set anytime a spi0 slav e detects a rising edge on nss while the receive buffer still holds unread data from a previous transfer. the new da ta is not transferred to the receive buffer, allowing the previous ly received data byte to be read. th e data byte causing th e overrun is lost. figure 19.3. full duplex operation receive buffer 0 1 2 3 4 5 6 7 spi shift register slave device mosi miso nss receive buffer 0 1 2 3 4 5 6 7 spi shift register master device mosi miso nss vdd baud rate generator sck sck px.y
c8051f020/1/2/3 200 rev. 1.4 multiple masters may reside on the same bus. a mode fault flag (modf, spi0cn.5) is set to logic 1 when spi0 is configured as a master (msten = 1) a nd its slave select signal nss is pulled low. when the mode fault flag is set, the msten and spien bits of the spi co ntrol register are cleared by hardwa re, thereby placing th e spi0 module in an "off-line" state. in a multiple-maste r environment, the system co ntroller should check the state of the slvsel flag (spi0cn.2) to ensure the bus is free before setting the msten bit and initiating a data transfer. 19.3. serial clock timing as shown in figure 19.4 , four combinations of serial clock phase and polarity can be selected using the clock control bits in the spi0 configuration register (spi0cfg). th e ckpha bit (spi0cfg.7) select s one of two clock phases (edge used to latch the data). the ckpol bit (spi0cfg.6) selects between an active-high or active-low clock. both master and slave devices must be configured to use the same clock phase and polarity. note: spi0 should be disabled (by clearing the spien bit, spi0cn.0) while changing the clock phase and polarity. the spi0 clock rate register (spi0ckr) as shown in figure 19.7 controls the master mode serial clock frequency. this register is ignored when operating in slave mode. figure 19.4. data/clock timing diagram miso/mosi nss sck (ckpol=0, ckpha=0) sck (ckpol=0, ckpha=1) sck (ckpol=1, ckpha=0) sck (ckpol=1, ckpha=1) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
c8051f020/1/2/3 rev. 1.4 201 19.4. spi special function registers spi0 is accessed and controlled through four special functi on registers in the system co ntroller: spi0cn control reg - ister, spi0dat data register, spi0cfg configuration regi ster, and spi0ckr clock rate register. the four special function registers related to the operation of the spi0 bus are described in the following section. figure 19.5. spi0cfg: spi0 configuration register bit7: ckpha: spi0 clock phase. this bit controls the spi0 clock phase. 0: data sampled on first edge of sck period. 1: data sampled on second edge of sck period. bit6: ckpol: spi0 clock polarity. this bit controls the spi0 clock polarity. 0: sck line low in idle state. 1: sck line high in idle state. bits5-3: bc2-bc0: spi0 bit count. indicates which of the up to 8 bits of the spi0 word have been transmitted. bits2-0: spifrs2-spifrs0: spi0 frame size. these three bits determine the number of bits to sh ift in/out of the spi0 shift register during a data transfer in master mode. they are ignored in slave mode. r/w r/w r r r r/w r/w r/w reset value ckpha ckpol bc2 bc1 bc0 spifrs2 spifrs1 spifrs0 00000111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x9a bc2-bc0 bit transmitted 000bit 0 (lsb) 001 bit 1 010 bit 2 011 bit 3 100 bit 4 101 bit 5 110 bit 6 111bit 7 (msb) spifrs bits shifted 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 8
c8051f020/1/2/3 202 rev. 1.4 figure 19.6. spi0cn: spi0 control register bit7: spif: spi0 interrupt flag. this bit is set to logic 1 by hardware at the end of a data transfer. if interrupts are enabled, setting this bit causes the cpu to vector to the spi0 interrupt se rvice routine. this bit is not automatically cleared by hardware. it must be cleared by software. bit6: wcol: write collision flag. this bit is set to logic 1 by hardware (and generate s a spi0 interrupt) to indi cate a write to the spi0 data register was attempted while a data transfer wa s in progress. if interrupts are enabled, setting this bit causes the cpu to vector to the spi0 interrupt se rvice routine. this bit is not automatically cleared by hardware. it must be cleared by software. bit5: modf: mode fault flag. this bit is set to logic 1 by hardware (and generates a spi0 interrupt) when a master mode collision is detected (nss is low and msten = 1). if interrupt s are enabled, setting th is bit causes the cpu to vector to the spi0 interrupt service routine. this bit is not automatically cleared by hardware. it must be cleared by software. bit4: rxovrn: receive overrun flag. this bit is set to logic 1 by hardware (and genera tes a spi0 interrupt) when the receive buffer still holds unread data from a previous tr ansfer and the last bit of the curr ent transfer is shifted into the spi0 shift register. if interrupts are enabled, setti ng this bit causes the cpu to vector to the spi0 inter- rupt service routine. this bit is not automatically cleared by hardware. it must be cleared by software. bit3: txbsy: transmit busy flag. this bit is set to logic 1 by hardware while a master mode transfer is in progres s. it is cleared by hard- ware at the end of the transfer. bit2: slvsel: slave selected flag. this bit is set to logic 1 whenever the nss pin is low indicating it is enabled as a slave. it is cleared to logic 0 when nss is high (slave disabled). bit1: msten: master mode enable. 0: disable master mode. operate in slave mode. 1: enable master mode . operate as a master. bit0: spien: spi0 enable. this bit enables/disables the spi. 0: spi disabled. r/w r/w r/w r/w r r r/w r/w reset value spif wcol modf rxovrn txbsy slvsel msten spien 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xf8
c8051f020/1/2/3 rev. 1.4 203 figure 19.7. spi0ckr: spi0 clock rate register bits7-0: scr7-scr0: spi0 clock rate these bits determine the frequency of the sck output when the spi0 module is configured for master mode operation. the sck clock frequency is a divided down version of the system clock, and is given in the following equation, where sysclk is the system clock frequency and spi0cr is the 8- bit value held in the spi0cr register. for 0 <= spi0ckr <= 255 example: if sysclk = 2 mhz and spi0ckr = 0x04, r/w r/w r/w r/w r/w r/w r/w r/w reset value scr7 scr6 scr5 scr4 scr3 scr2 scr1 scr0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x9d f sck sysclk 2 spi 0 ckr 1 + () ---------------- ------------------ -------------- - = f sck 2000000 241 + () ---------------- ---------- = f sck 200 khz = figure 19.8. spi0dat: spi0 data register bits7-0: spi0dat: spi0 transmit and receive data. the spi0dat register is used to transmit and recei ve spi0 data. wr iting data to sp i0dat places the data immediately into the shift register and initia tes a transfer when in master mode. a read of spi0dat returns the conten ts of the receive buffer. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x9b
c8051f020/1/2/3 204 rev. 1.4 notes
c8051f020/1/2/3 rev. 1.4 205 20. uart0 uart0 is an enhanced serial port with frame error de tection and address recognition hardware. uart0 may operate in full-duplex asynchronous or half -duplex synchronous modes, and mutip roccessor communication is fully sup - ported. receive data is buffered in a holding register, al lowing uart0 to start reception of a second incoming data byte before software has finished reading the previous da ta byte. a receive overrun bit indicates when new received data is latched into the receive buffer be fore the previous r eceived byte is read. uart0 is accessed via its associated sfrs, serial control (scon0) and serial data buffer (sbuf0). the single sbuf0 location provides access to both transmit and receive registers. read s access the receive register and writes access the transmit regi ster automatically. uart0 may be operated in polled or interrupt mode. uart0 has two sources of interrupts: a transmit interrupt flag, ti0 (scon0.1) set when transmission of a data byte is complete, a nd a receive interrupt flag, ri0 (scon0.0) set when reception of a data byte is complete. uart0 interrup t flags are not cleared by ha rdware when the cpu vectors to the interrupt service routine; they must be cleared manually by software. th is allows software to determine the cause of the uart0 interrupt (trans mit complete or receive complete). figure 20.1. uart0 block diagram tx control tx clock tx irq zero detector send shift set q d clr stop bit gen. tb8 start data write to sbuf crossbar tx port i/o serial port (uart0/1) interrupt ti ri scon s m 2 t b 8 r b 8 t i r i s m 1 s m 0 r e n rx control start rx clock load sbuf 0x1ff shift en rx irq uart baud rate generation logic sfr bus input shift register (9 bits) frame error detection sbuf (receive latch) read sbuf sfr bus saddr saden match detect rb8 load sbuf crossbar rx sbuf (transmit shift) address match
c8051f020/1/2/3 206 rev. 1.4 20.1. uart0 operational modes uart0 provides four operating modes (one synchronous and three asynchrono us) selected by setting configuration bits in the scon0 register. these four modes offer different baud rates and communication protocols. the four modes are summarized in table 20.1 . 20.1.1. mode 0: synchronous mode mode 0 provides synchronous, half-duple x communication. serial data is tran smitted and received on the rx0 pin. the tx0 pin provides the shift clock for both transmit and receive. the mcu must be th e master since it generates the shift clock for transmission in both di rections (see the interconnect diagram in figure 20.2 ). data transmission begins when an instru ction writes a data byte to the sbuf0 re gister. eight data bits are transferred lsb first (see the timing diagram in figure 20.3 ), and the ti0 transmit interrupt fl ag (scon0.1) is set at the end of the eighth bit time. data recep tion begins when the ren0 receive enable bi t (scon0.4) is set to logic 1 and the ri0 receive interrupt flag (s con0.0) is cleared. one cycle afte r the eighth bit is shifted in , the ri0 flag is set and recep - tion stops until software clears the ri0 bit. an interrupt will occur if enab led when either ti0 or ri0 are set. the mode 0 baud rate is sysclk / 12. rx0 is forced to open-drain in mode 0, and an external pull-up will typically be required. table 20.1. uart0 modes mode synchronization baud clock data bits start/stop bits 0 synchronous sysclk / 12 8 none 1 asynchronous timer 1 or 2 overflow 8 1 start, 1 stop 2 asynchronous sysclk / 32 or sysclk / 64 9 1 start, 1 stop 3 asynchronous timer 1 or 2 overflow 9 1 start, 1 stop figure 20.2. uart0 mode 0 interconnect shift reg. clk c8051fxxx rx tx data 8 extra outputs figure 20.3. uart0 mode 0 timing diagram d0 mode 0 receive rx (data in) d1 d2 d3 d4 d5 d6 d7 tx (clk out) d1 d0 d2 d3 d4 d5 d6 d7 rx (data out) mode 0 transmit tx (clk out)
c8051f020/1/2/3 rev. 1.4 207 20.1.2. mode 1: 8-bit uart, variable baud rate mode 1 provides standard asynchronous, full duplex communi cation using a total of 10 bits per data byte: one start bit, eight data bits (lsb fi rst), and one stop bit. data are transmitted from the tx0 pi n and received at the rx0 pin. on receive, the eight data bits are stored in sbuf0 and the stop bit goes into rb80 (scon0.2). data transmission begins when an instruction writes a da ta byte to the sbuf0 register. the ti0 transmit interrupt flag (scon0.1) is set at the end of the transmission (the beginning of the stop-bit time). data reception can begin any time after the ren0 receive enable bi t (scon0.4) is set to logic 1. after th e stop bit is received, the data byte will be loaded into the sbuf0 receive register if the following conditions are met: ri0 must be logic 0, and if sm20 is logic 1, the stop bit must be logic 1. if these conditions are met, the eight bits of data are stored in sbuf0, th e stop bit is stored in rb80 and the ri0 flag is set. if these conditions are not met, sbuf0 and rb80 will not be loaded and the ri0 flag will not be set. an inter - rupt will occur if enabled when either ti0 or ri0 is set. the baud rate generated in mode 1 is a function of timer overflow, shown in equation 20.1 and equation 20.2 . uart0 can use timer 1 operating in 8-bit auto-reload mode , or timer 2 operating in baud rate generator mode to generate the baud rate (note that the tx and rx clocks ar e selected separately). on each timer overflow event (a roll - over from all ones - (0xff for timer 1, 0xffff for timer 2) - to zero) a clock is sent to the baud rate logic. timer 2 is selected as tx and/or rx baud clock sour ce by setting the tclk0 (t2con.4) and/or rclk0 (t2con.5) bits, respectively (see section ?22. timers? on page 225 for complete timer configur ation details). when either tclk0 or rclk0 is set to logic 1, timer 2 is forced into baud rate generator mode , with sysclk / 2 as its clock source. if tclk0 and/or rclk0 is logic 0, timer 1 acts as the baud clock source for the tx and/or rx circuits, respectively. the mode 1 baud rate equations are shown below, where t1m is the timer 1 clock select bit (register ckcon), th1 is the 8-bit reload register for timer 1, smod0 is the uart0 baud rate doubler (register pcon) and [rcap2h , rcap2l] is the 16-bit reload register for timer 2. figure 20.4. uart0 mode 1 timing diagram d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space equation 20.1. mode 1 baud rate using timer 1 baudrate 2 smod 0 32 ------------------ - ?? ?? sysclk 12 t 1 m 1 ) ? () 256 th 1 ? () --------------------- --------------------- -------------- ?? ?? = equation 20.2. mode 1 baud rate using timer 2 baudrate sysclk 32 65536 rcap 2 hrcap 2 l [, ] ? () ------------------- --------------------- ----------------- ------------------ ----------------- - =
c8051f020/1/2/3 208 rev. 1.4 20.1.3. mode 2: 9-bit uart, fixed baud rate mode 2 provides asynchronous, full-duplex communication using a total of eleven bits per data byte: a start bit, 8 data bits (lsb first), a programmable ninth data bit, and a st op bit. mode 2 supports multiprocessor communications and hardware address recognition (see section ?20.2. multiprocessor communications? on page 210 ). on transmit, the ninth data bit is determined by the value in tb80 (scon0 .3). it can be assigned the va lue of the parity flag p in the psw or used in multipro cessor communications. on receive, the nint h data bit goes into rb80 (scon0.2) and the stop bit is ignored. data transmission begins when an instruction writes a da ta byte to the sbuf0 register. the ti0 transmit interrupt flag (scon0.1) is set at the end of the transmission (the beginning of the stop-bit time). data reception can begin any time after the ren0 receive enable bi t (scon0.4) is set to logic 1. after th e stop bit is received, the data byte will be loaded into the sbuf0 receive register if ri0 is logic 0 and one of the following re quirements are met: 1. sm20 is logic 0 2. sm20 is logic 1, the received 9th bit is logic 1, and the received address matches the uart0 address as described in section 20.2 . if the above conditions are satisfied, the eight bits of data are stored in sbuf0, the ninth bit is stored in rb80 and the ri0 flag is set. if these conditions ar e not met, sbuf0 and rb80 will not be loaded and the ri0 flag will not be set. an interrupt will occur if enable d when either ti0 or ri0 is set. the baud rate in mode 2 is either sysclk / 32 or sysclk / 64, depending on the value of the smod0 bit in regis - ter pcon. equation 20.3. mode 2 baud rate baudrate 2 smod 0 sysclk 64 ------------ --------- - ?? ?? = figure 20.5. uart modes 2 and 3 timing diagram d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space d8
c8051f020/1/2/3 rev. 1.4 209 20.1.4. mode 3: 9-bit uart, variable baud rate mode 3 uses the mode 2 transmission protocol with the mode 1 baud rate generation. mode 3 operation transmits 11 bits: a start bit, 8 data bits (lsb firs t), a programmable ninth data bit, and a stop bit. the baud rate is derived from timer 1 or timer 2 overflows, as defined by equation 20.1 and equation 20.2 . multiprocessor communications and hardware address recognition are supported, as described in section 20.2 . f i gure 20 . 6 . u a rt modes 1 , 2 , and 3 interconnect d i agram or rs-232 c8051fxxx rs-232 level xltr tx rx c8051fxxx rx tx mcu rx tx
c8051f020/1/2/3 210 rev. 1.4 20.2. multiprocessor communications modes 2 and 3 support multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit and the built-in uart 0 address recognition hardware. a master processor begins a transfer with an address byte to select one or more target slave devices. an address byte differs from a data byte in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0. the uart0 address is configured via two sfrs: saddr0 (s erial address) and saden0 (serial address enable). saden0 sets the bit mask for the address held in saddr0 : bits set to logic 1 in saden0 correspond to bits in saddr0 that are checked against the r eceived address byte; bits set to logi c 0 in saden0 correspond to ?don?t care? bits in saddr0. setting the sm20 bit (s con0.5) configures uart0 such that when a st op bit is received, uart0 will generate an interrupt only if the ninth b it is logic 1 (rb80 = 1) and the received data byte matches the uart0 slave address. fol - lowing the received address in terrupt, the slave should clear its sm20 bit to enable inte rrupts on the reception of the following data byte(s). once the entire message is received , the addressed slave should reset its sm20 bit to ignore all transmissions until it receives the next address byte. while sm20 is logic 1, uart0 i gnores all bytes that do not match the uart0 address and includ e a ninth bit that is logic 1. multiple addresses can be assigned to a single slave and/ or a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. the broadcast address is the logi - cal or of registers saddr0 and saden0, and ?0?s of the re sult are treated as ?don?t cares?. typically a broadcast address of 0xff (hexadecimal) is ackno wledged by all slaves, assuming ?don?t care? bits as ?1?s. the master proces - sor can be configured to receive all tran smissions or a protocol can be implemented such that the master/slave role is temporarily reversed to enable half-duplex transm ission between the origin al master and slave(s). example 1 example 2 example 3 saddr0 = 00110101 saddr0 = 00110101 saddr0 = 00110101 saden0 = 00001111 saden0 = 11110011 saden0 = 110 00000 uart0 address = xxxx0101 uart0 address = 0011xx01 uart0 address = 00xxxxxx figure 20.7. uart multi-processo r mode interconnect diagram master device slave device tx rx rx tx slave device rx tx slave device rx tx +5v
c8051f020/1/2/3 rev. 1.4 211 20.3. frame and transmission error detection frame error detection is available in th e following modes when the sstat0 bit in register pcon is set to logic 1. note: the sstat0 bit must be logic 1 to access any of th e status bits (fe0, rxovr0, and txcol0). to access the uart0 mode select bits (sm00, sm10, and sm20), the sstat0 bit must be logic 0. all modes: the transmit collision bit (txcol0 bit in register scon0) r eads ?1? if user software writes data to the sbuf0 reg - ister while a transmit is in progress. note that the txcol0 bit also functions as the sm20 bit when the sstat0 bit in register pcon is logic 0. modes 1, 2, and 3: the receive overrun bit (rxovr0 in register scon0) reads ?1? if a new data byte is latched into the receive buffer before software has read the previous byte. note that the rxovr0 bit also functions as the sm10 bit when the sstat0 bit in register pcon is logic 0. the frame error bit (fe0 in register sc on0) reads ?1? if an invalid (low) stop bit is detected. note that the fe0 bit also functions as the sm00 bit when the sstat0 bit in register pcon is logic 0.
c8051f020/1/2/3 212 rev. 1.4 table 20.2. oscillator frequencies for standard baud rates oscillator frequency (mhz) divide factor timer 1 load value* resulting baud rate (hz)** 25.0 434 0xe5 57600 (57870) 25.0 868 0xca 28800 24.576 320 0xec 76800 24.576 848 0xcb 28800 (28921) 24.0 208 0xf3 115200 (115384) 24.0 833 0xcc 28800 (28846) 23.592 205 0xf3 115200 (113423) 23.592 819 0xcd 28800 (28911) 22.1184 192 0xf4 115200 22.1184 768 0xd0 28800 18.432 160 0xf6 115200 18.432 640 0xd8 28800 16.5888 144 0xf7 115200 16.5888 576 0xdc 28800 14.7456 128 0xf8 115200 14.7456 512 0xe0 28800 12.9024 112 0xf9 115200 12.9024 448 0xe4 28800 11.0592 96 0xfa 115200 11.0592 348 0xe8 28800 9.216 80 0xfb 115200 9.216 320 0xec 28800 7.3728 64 0xfc 115200 7.3728 256 0xf0 28800 5.5296 48 0xfd 115200 5.5296 192 0xf4 28800 3.6864 32 0xfe 115200 3.6864 128 0xf8 28800 1.8432 16 0xff 115200 1.8432 64 0xfc 28800 * assumes smod0=1 and t1m=1. ** numbers in parenthesis show the actual baud rate.
c8051f020/1/2/3 rev. 1.4 213 figure 20.8. scon0: uart0 control register bits7-6: the function of these bits is determined by the sstat0 bit in register pcon. if sstat0 is logic 1, these bits are uart0 status indicators as described in section 20.3 . if sstat0 is logic 0, these bits select the serial port operation mode as shown below. sm00-sm10: serial po rt operation mode: bit5: sm20: multiprocessor communication enable. if sstat0 is logic 1, this bit is a ua rt0 status indicator as described in section 20.3 . if sstat0 is logic 0, the function of this bit is dependent on the serial port operation mode. mode 0: no effect. mode 1: checks for valid stop bit. 0: logic level of stop bit is ignored. 1: ri0 will only be activated if stop bit is logic level 1. modes 2 and 3: multiprocessor communications enable. 0: logic level of ninth bit is ignored. 1: ri0 is set and an interrupt is generated only when the ninth bit is logic 1 and the received address matches the uart0 address or the broadcast address. bit4: ren0: receive enable. this bit enables/disables the uart0 receiver. 0: uart0 reception disabled. 1: uart0 reception enabled. bit3: tb80: ninth transmission bit. the logic level of this bit will be assigned to the ninth transmission bit in modes 2 and 3. it is not used in modes 0 and 1. set or cleared by software as required. bit2: rb80: ninth receive bit. the bit is assigned the logic level of the ninth bit received in modes 2 and 3. in mode 1, if sm20 is logic 0, rb80 is assigned the logic level of th e received stop bit. rb8 is not used in mode 0. bit1: ti0: transmit interrupt flag. set by hardware when a byte of data has been tran smitted by uart0 (after the 8th bit in mode 0, or at the beginning of the stop bit in other modes). when the uart0 interrupt is enabled, setting this bit causes the cpu to vector to the uar t0 interrupt service routine. this bit must be cleared manually by software bit0: ri0: receive interrupt flag. set by hardware when a byte of data has been received by uart0 (as selected by the sm20 bit). when the uart0 interrupt is enabled, setting this bit causes the cpu to vector to the uart0 inter- rupt service routine. this bit must be cleared manually by software. r/w r/w r/w r/w r/w r/w r/w r/w reset value sm00/fe0 sm10/rxov0 sm20/txcol0 ren0 tb80 rb80 ti0 ri0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x98 sm00 sm10 mode 0 0 mode 0: synchronous mode 0 1 mode 1: 8-bit uart, variable baud rate 1 0 mode 2: 9-bit uart, fixed baud rate 1 1 mode 3: 9-bit uart, variable baud rate
c8051f020/1/2/3 214 rev. 1.4 figure 20.9. sbuf0: uart0 data buffer register bits7-0: sbuf0.[7:0]: uart0 buffer bits 7-0 (msb-lsb) this sfr accesses two registers; a transmit shift re gister and a receive latch register. when data is written to sbuf0, it goes to the transmit shift register and is held for serial transmission. writing a byte to sbuf0 is what initiates the transmission. a read of sbuf0 returns the contents of the receive latch. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x99 figure 20.10. saddr0: uart0 slave address register bits7-0: saddr0.[7:0]: uart0 slave address the contents of this register are used to define the uart0 slave ad dress. register saden0 is a bit mask to determine which bits of saddr0 are checked against a recei ved address: corr esponding bits set to logic 1 in saden0 are checked; corresponding bits set to logic 0 are ?don?t cares?. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa9 figure 20.11. saden0: uart0 slave address enable register bits7-0: saden0.[7:0]: uart0 slave address enable bits in this register enable corresponding bits in register saddr0 to determine the uart0 slave address. 0: corresponding bit in saddr0 is a ?don?t care?. 1: corresponding bit in saddr0 is checked against a received address. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb9
c8051f020/1/2/3 rev. 1.4 215 21. uart1 uart1 is an enhanced serial port with frame error de tection and address recognition hardware. uart1 may operate in full-duplex asynchronous or half -duplex synchronous modes, and mutip roccessor communication is fully sup - ported. receive data is buffered in a holding register, al lowing uart1 to start reception of a second incoming data byte before software has finished reading the previous da ta byte. a receive overrun bit indicates when new received data is latched into the receive buffer be fore the previous r eceived byte is read. uart1 is accessed via its associated sfrs, serial control (scon1) and serial data buffer (sbuf1). the single sbuf1 location provides access to both transmit and receive registers. read s access the receive register and writes access the transmit regi ster automatically. uart1 may be operated in polled or interrupt mode. uart1 has two sources of interrupts: a transmit interrupt flag, ti1 (scon1.1) set when transmission of a data byte is complete, a nd a receive interrupt flag, ri1 (scon1.0) set when reception of a data byte is complete. uart1 interrup t flags are not cleared by ha rdware when the cpu vectors to the interrupt service routine; they must be cleared manually by software. th is allows software to determine the cause of the uart1 interrupt (trans mit complete or receive complete). figure 21.1. uart1 block diagram tx control tx clock tx irq zero detector send shift set q d clr stop bit gen. tb8 start data write to sbuf crossbar tx port i/o serial port (uart0/1) interrupt ti ri scon s m 2 t b 8 r b 8 t i r i s m 1 s m 0 r e n rx control start rx clock load sbuf 0x1ff shift en rx irq uart baud rate generation logic sfr bus input shift register (9 bits) frame error detection sbuf (receive latch) read sbuf sfr bus saddr saden match detect rb8 load sbuf crossbar rx sbuf (transmit shift) address match
c8051f020/1/2/3 216 rev. 1.4 21.1. uart1 operational modes uart1 provides four operating modes (one synchronous and three asynchrono us) selected by setting configuration bits in the scon1 register. these four modes offer different baud rates and communication protocols. the four modes are summarized in table 21.1 . 21.1.1. mode 0: synchronous mode mode 0 provides synchronous, half-duple x communication. serial data is tran smitted and received on the rx1 pin. the tx1 pin provides the shift clock for both transmit and receive. the mcu must be th e master since it generates the shift clock for transmission in both di rections (see the interconnect diagram in figure 21.2 ). data transmission begins when an instru ction writes a data byte to the sbuf1 re gister. eight data bits are transferred lsb first (see the timing diagram in figure 21.3 ), and the ti1 transmit interrupt fl ag (scon1.1) is set at the end of the eighth bit time. data recep tion begins when the ren1 receive enable bi t (scon1.4) is set to logic 1 and the ri1 receive interrupt flag (s con1.0) is cleared. one cycle afte r the eighth bit is shifted in , the ri1 flag is set and recep - tion stops until software clears the ri1 bit. an interrupt will occur if enab led when either ti1 or ri1 are set. the mode 0 baud rate is sysclk / 12. rx1 is forced to open-drain in mode 0, and an external pull-up will typically be required. table 21.1. uart1 modes mode synchronization baud clock data bits start/stop bits 0 synchronous sysclk / 12 8 none 1 asynchronous timer 1 or 4 overflow 8 1 start, 1 stop 2 asynchronous sysclk / 32 or sysclk / 64 9 1 start, 1 stop 3 asynchronous timer 1 or 4 overflow 9 1 start, 1 stop figure 21.2. uart1 mode 0 interconnect shift reg. clk c8051fxxx rx tx data 8 extra outputs figure 21.3. uart1 mode 0 timing diagram d0 mode 0 receive rx (data in) d1 d2 d3 d4 d5 d6 d7 tx (clk out) d1 d0 d2 d3 d4 d5 d6 d7 rx (data out) mode 0 transmit tx (clk out)
c8051f020/1/2/3 rev. 1.4 217 21.1.2. mode 1: 8-bit uart, variable baud rate mode 1 provides standard asynchronous, full duplex communi cation using a total of 10 bits per data byte: one start bit, eight data bits (lsb fi rst), and one stop bit. data are transmitted from the tx1 pi n and received at the rx1 pin. on receive, the eight data bits are stored in sbuf1 and the stop bit goes into rb81 (scon1.2). data transmission begins when an instruction writes a da ta byte to the sbuf1 register. the ti1 transmit interrupt flag (scon1.1) is set at the end of the transmission (the beginning of the stop-bit time). data reception can begin any time after the ren1 receive enable bi t (scon1.4) is set to logic 1. after th e stop bit is received, the data byte will be loaded into the sbuf1 receive register if the following conditions are met: ri1 must be logic 0, and if sm21 is logic 1, the stop bit must be logic 1. if these conditions are met, the eight bits of data are stored in sbuf1, th e stop bit is stored in rb81 and the ri1 flag is set. if these conditions are not met, sbuf1 and rb81 will not be loaded and the ri1 flag will not be set. an inter - rupt will occur if enabled when either ti1 or ri1 is set. the baud rate generated in mode 1 is a function of timer overflow, shown in equation 21.1 and equation 21.2 . uart1 can use timer 1 operating in 8-bit auto-reload mode , or timer 4 operating in baud rate generator mode to generate the baud rate (note that the tx and rx clocks ar e selected separately). on each timer overflow event (a roll - over from all ones - (0xff for timer 1, 0xffff for timer 4) - to zero) a clock is sent to the baud rate logic. timer 4 is selected as tx and/or rx baud clock sour ce by setting the tclk1 (t4con.4) and/or rclk1 (t4con.5) bits, respectively (see section ?22. timers? on page 225 for complete timer configur ation details). when either tclk1 or rclk1 is set to logic 1, timer 4 is forced into baud rate generator mode , with sysclk / 2 as its clock source. if tclk1 and/or rclk1 is logic 0, timer 1 acts as the baud clock source for the tx and/or rx circuits, respectively. the mode 1 baud rate equations are shown below, where t1m is the timer 1 clock select bit (register ckcon), th1 is the 8-bit reload register for timer 1, smod1 is the uart1 baud rate doubler (register pcon), and [rcap4h , rcap4l] is the 16-bit reload register for timer 4. figure 21.4. uart1 mode 1 timing diagram d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space equation 21.1. mode 1 baud rate using timer 1 baudrate 2 smod 1 32 ------------------ - ?? ?? sysclk 12 t 1 m 1 ) ? () 256 th 1 ? () --------------------- --------------------- -------------- ?? ?? = equation 21.2. mode 1 baud rate using timer 4 baudrate sysclk 32 65536 rcap 4 hrcap 4 l [, ] ? () [] --------------------- --------------------- ---------------------- ----------------- ---------------- - =
c8051f020/1/2/3 218 rev. 1.4 21.1.3. mode 2: 9-bit uart, fixed baud rate mode 2 provides asynchronous, full-duplex communication using a total of eleven bits per data byte: a start bit, 8 data bits (lsb first), a programmable ninth data bit, and a st op bit. mode 2 supports multiprocessor communications and hardware address recognition (see section ?21.2. multiprocessor communications? on page 220 ). on transmit, the ninth data bit is determined by the value in tb81 (scon1 .3). it can be assigned the va lue of the parity flag p in the psw or used in multipro cessor communications. on receive, the nint h data bit goes into rb81 (scon1.2) and the stop bit is ignored. data transmission begins when an instruction writes a da ta byte to the sbuf1 register. the ti1 transmit interrupt flag (scon1.1) is set at the end of the transmission (the beginning of the stop-bit time). data reception can begin any time after the ren1 receive enable bi t (scon1.4) is set to logic 1. after th e stop bit is received, the data byte will be loaded into the sbuf1 receive register if ri1 is logic 0 and one of the following re quirements are met: 1. sm21 is logic 0 2. sm21 is logic 1, the received 9th bit is logic 1, and the received address matches the uart1 address as described in section 21.2 . if the above conditions are satisfied, the eight bits of data are stored in sbuf1, the ninth bit is stored in rb81 and the ri1 flag is set. if these conditions ar e not met, sbuf1 and rb81 will not be loaded and the ri1 flag will not be set. an interrupt will occur if enable d when either ti1 or ri1 is set. the baud rate in mode 2 is either sysclk / 32 or sysclk / 64, depending on the value of the smod1 bit in regis - ter pcon. equation 21.3. mode 2 baud rate baudrate 2 smod 1 sysclk 64 ------------ --------- - ?? ?? = figure 21.5. uart modes 2 and 3 timing diagram d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space d8
c8051f020/1/2/3 rev. 1.4 219 21.1.4. mode 3: 9-bit uart, variable baud rate mode 3 uses the mode 2 transmission protocol with the mode 1 baud rate generation. mode 3 operation transmits 11 bits: a start bit, 8 data bits (lsb firs t), a programmable ninth data bit, and a stop bit. the baud rate is derived from timer 1 or timer 4 overflows, as defined by equation 21.1 and equation 21.2 . multiprocessor communications and hardware address recognition are supported, as described in section 21.2 . f i gure 21 . 6 . u a rt modes 1 , 2 , and 3 interconnect d i agram or rs-232 c8051fxxx rs-232 level xltr tx rx c8051fxxx rx tx mcu rx tx
c8051f020/1/2/3 220 rev. 1.4 21.2. multiprocessor communications modes 2 and 3 support multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit and the built-in uart 1 address recognition hardware. a master processor begins a transfer with an address byte to select one or more target slave devices. an address byte differs from a data byte in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0. the uart1 address is configured via two sfrs: saddr1 (s erial address) and saden1 (serial address enable). saden1 sets the bit mask for the address held in saddr1 : bits set to logic 1 in saden1 correspond to bits in saddr1 that are checked against the r eceived address byte; bits set to logi c 0 in saden1 correspond to ?don?t care? bits in saddr1. setting the sm21 bit (s con1.5) configures uart1 such that when a st op bit is received, uart1 will generate an interrupt only if the ninth b it is logic 1 (rb81 = 1) and the received data byte matches the uart1 slave address. fol - lowing the received address in terrupt, the slave should clear its sm21 bit to enable inte rrupts on the reception of the following data byte(s). once the entire message is received , the addressed slave should reset its sm21 bit to ignore all transmissions until it receives the next address byte. while sm21 is logic 1, uart1 i gnores all bytes that do not match the uart1 address and includ e a ninth bit that is logic 1. multiple addresses can be assigned to a single slave and/ or a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. the broadcast address is the logi - cal or of registers saddr1 and saden1, and ?0?s of the re sult are treated as ?don?t cares?. typically a broadcast address of 0xff (hexadecimal) is ackno wledged by all slaves, assuming ?don?t care? bits as ?1?s. the master proces - sor can be configured to receive all tran smissions or a protocol can be implemented such that the master/slave role is temporarily reversed to enable half-duplex transm ission between the origin al master and slave(s). example 1 example 2 example 3 saddr1 = 00110101 saddr1 = 00110101 saddr1 = 00110101 saden1 = 00001111 saden1 = 11110011 saden1 = 110 00000 uart1 address = xxxx0101 uart1 address = 0011xx01 uart1 address = 00xxxxxx figure 21.7. uart multi-processo r mode interconnect diagram master device slave device tx rx rx tx slave device rx tx slave device rx tx +5v
c8051f020/1/2/3 rev. 1.4 221 21.3. frame and transmission error detection frame error detection is available in th e following modes when the sstat1 bit in register pcon is set to logic 1. note: the sstat1 bit must be logic 1 to access any of th e status bits (fe1, rxovr1, and txcol1). to access the uart1 mode select bits (sm01, sm11, and sm21), the sstat1 bit must be logic 0. all modes: the transmit collision bit (txcol1 bit in register scon1) r eads ?1? if user software writes data to the sbuf1 reg - ister while a transmit is in progress. note that the txcol1 bit also functions as the sm21 bit when the sstat1 bit in register pcon is logic 0. modes 1, 2, and 3: the receive overrun bit (rxovr1 in register scon1) reads ?1? if a new data byte is latched into the receive buffer before software has read the previous byte. note that the rxovr1 bit also functions as the sm11 bit when the sstat1 bit in register pcon is logic 0. the frame error bit (fe1 in register sc on1) reads ?1? if an invalid (low) stop bit is detected. note that the fe1 bit also functions as the sm01 bit when the sstat1 bit in register pcon is logic 0.
c8051f020/1/2/3 222 rev. 1.4 table 21.2. oscillator frequencies for standard baud rates oscillator frequency (mhz) divide factor timer 1 load value* resulting baud rate (hz)** 25.0 434 0xe5 57600 (57870) 25.0 868 0xca 28800 24.576 320 0xec 76800 24.576 848 0xcb 28800 (28921) 24.0 208 0xf3 115200 (115384) 24.0 833 0xcc 28800 (28846) 23.592 205 0xf3 115200 (113423) 23.592 819 0xcd 28800 (28911) 22.1184 192 0xf4 115200 22.1184 768 0xd0 28800 18.432 160 0xf6 115200 18.432 640 0xd8 28800 16.5888 144 0xf7 115200 16.5888 576 0xdc 28800 14.7456 128 0xf8 115200 14.7456 512 0xe0 28800 12.9024 112 0xf9 115200 12.9024 448 0xe4 28800 11.0592 96 0xfa 115200 11.0592 348 0xe8 28800 9.216 80 0xfb 115200 9.216 320 0xec 28800 7.3728 64 0xfc 115200 7.3728 256 0xf0 28800 5.5296 48 0xfd 115200 5.5296 192 0xf4 28800 3.6864 32 0xfe 115200 3.6864 128 0xf8 28800 1.8432 16 0xff 115200 1.8432 64 0xfc 28800 * assumes smod1=1 and t1m=1. ** numbers in parenthesis show the actual baud rate.
c8051f020/1/2/3 rev. 1.4 223 figure 21.8. scon1: uart1 control register bits7-6: the function of these bits is determined by the sstat1 bit in register pcon. if sstat1 is logic 1, these bits are uart1 status indicators as described in section 21.3 . if sstat1 is logic 0, these bits select the serial port operation mode as shown below. sm01-sm11: serial po rt operation mode: bit5: sm21: multiprocessor communication enable. if sstat1 is logic 1, this bit is a ua rt1 status indicator as described in section 21.3 . if sstat1 is logic 0, the function of this bit is dependent on the serial port operation mode. mode 0: no effect. mode 1: checks for valid stop bit. 0: logic level of stop bit is ignored. 1: ri1 will only be activated if stop bit is logic level 1. modes 2 and 3: multiprocessor communications enable. 0: logic level of ninth bit is ignored. 1: ri1 is set and an interrupt is generated only when the ninth bit is logic 1 and the received address matches the uart1 address or the broadcast address. bit4: ren1: receive enable. this bit enables/disables the uart1 receiver. 0: uart1 reception disabled. 1: uart1 reception enabled. bit3: tb81: ninth transmission bit. the logic level of this bit will be assigned to the ninth transmission bit in modes 2 and 3. it is not used in modes 0 and 1. set or cleared by software as required. bit2: rb81: ninth receive bit. the bit is assigned the logic level of the ninth bit received in modes 2 and 3. in mode 1, if sm21 is logic 0, rb81 is assigned the logic level of th e received stop bit. rb8 is not used in mode 0. bit1: ti1: transmit interrupt flag. set by hardware when a byte of data has been tran smitted by uart1 (after the 8th bit in mode 0, or at the beginning of the stop bit in other modes). when the uart1 interrupt is enabled, setting this bit causes the cpu to vector to the uar t1 interrupt service routine. this bit must be cleared manually by software bit0: ri1: receive interrupt flag. set by hardware when a byte of data has been received by uart1 (as selected by the sm21 bit). when the uart1 interrupt is enabled, setting this bit causes the cpu to vector to the uart1 inter- rupt service routine. this bit must be cleared manually by software. r/w r/w r/w r/w r/w r/w r/w r/w reset value sm01/fe1 sm11/rxov1 sm21/txcol1 ren1 tb81 rb81 ti1 ri1 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf1 sm01 sm11 mode 0 0 mode 0: synchronous mode 0 1 mode 1: 8-bit uart, variable baud rate 1 0 mode 2: 9-bit uart, fixed baud rate 1 1 mode 3: 9-bit uart, variable baud rate
c8051f020/1/2/3 224 rev. 1.4 figure 21.9. sbuf1: uart1 data buffer register bits7-0: sbuf1.[7:0]: uart1 buffer bits 7-0 (msb-lsb) this sfr accesses two registers; a transmit shift re gister and a receive latch register. when data is written to sbuf1, it goes to the transmit shift register and is held for serial transmission. writing a byte to sbuf1 is what initiates the transmission. a read of sbuf1 returns the contents of the receive latch. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf2 figure 21.10. saddr1: uart1 slave address register bits7-0: saddr1.[7:0]: uart1 slave address the contents of this register are used to define the uart1 slave ad dress. register saden1 is a bit mask to determine which bits of saddr1 are checked against a recei ved address: corr esponding bits set to logic 1 in saden1 are checked; corresponding bits set to logic 0 are ?don?t cares?. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf3 figure 21.11. saden1: uart1 slave address enable register bits7-0: saden1.[7:0]: uart1 slave address enable bits in this register enable corresponding bits in register saddr1 to determine the uart1 slave address. 0: corresponding bit in saddr1 is a ?don?t care?. 1: corresponding bit in saddr1 is checked against a received address. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xae
c8051f020/1/2/3 rev. 1.4 225 22. timers the c8051f020/1/2/3 devices contain 5 counter/timers: thr ee are 16-bit counter /timers compatible with those found in the standard 8051, and two are 16-bit auto-reload time rs for use with the adcs, smbus, uart1, or for general purpose use. these can be used to measure time intervals, count external events and ge nerate periodic interrupt requests. timer 0 and timer 1 are nearly identical and have four primary modes of operation. timer 2 offers addi - tional capabilities not available in timers 0 and 1. timer 3 is similar to timer 2, but without the capture or baud rate generator modes. timer 4 is identical to timer 2, and can supply baud-rate generation capabilities to uart1. when functioning as a timer, the coun ter/timer registers are incremented on ea ch clock tick. clock ticks are derived from the system clock divided by either one or twelve as specified by the timer clock select bits (t4m-t0m) in ckcon, shown in figure 22.1 . the twelve-clocks-per-tick option provides compatibility with the older generation of the 8051 family. applications that require a faster timer can use the one-clock-per-tick option. when functioning as a counter, a counte r/timer register is increm ented on each high-to-low transition at the selected input pin. events with a frequency of up to one-fourth the system clock's frequency can be counted. the input signal need not be periodic, but it should be held at a given level fo r at least two full system clock cycles to ensure the level is sampled. timer 0 and timer 1: timer 2: timer 3: timer 4 13-bit counter/timer 16-bit counter/timer with auto-reload 16-bit timer with auto- reload 16-bit counter/timer with auto-reload 16-bit counter/timer 16-bit counter/timer with capture 16-bit counter/timer with capture 8-bit counter/timer with auto-reload baud rate generator for uart0 baud rate generator for uart1 two 8-bit counter/timers (timer 0 only)
c8051f020/1/2/3 226 rev. 1.4 figure 22.1. ckcon: clock control register bit7: unused. read = 0b, write = don?t care. bit6: t4m: timer 4 clock select. this bit controls the division of the system clock supplied to timer 4. this bit is ignored when the timer is in baud rate generator mode or counter mode (i.e. c/t4 = 1). 0: timer 4 uses the system clock divided by 12. 1: timer 4 uses the system clock. bit5: t2m: timer 2 clock select. this bit controls the division of the system clock supplied to timer 2. this bit is ignored when the timer is in baud rate generator mode or counter mode (i.e. c/t2 = 1). 0: timer 2 uses the system clock divided by 12. 1: timer 2 uses the system clock. bit4: t1m: timer 1 clock select. this bit controls the division of the system clock supplied to timer 1. 0: timer 1 uses the system clock divided by 12. 1: timer 1 uses the system clock. bit3: t0m: timer 0 clock select. this bit controls the division of the system clock supplied to counter/timer 0. 0: counter/timer uses the system clock divided by 12. 1: counter/timer uses the system clock. bits2-0: reserved. read = 000b, must write = 000. r/w r/w r/w r/w r/w r/w r/w r/w reset value - t4m t2m t1m t0m reserved reserved reserved 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8e
c8051f020/1/2/3 rev. 1.4 227 22.1. timer 0 and timer 1 timer 0 and timer 1 are accessed and controlled through sfrs. each counter/timer is impleme nted as a 16-bit regis - ter accessed as two separate bytes: a low byte (tl0 or tl1 ) and a high byte (th0 or th1). the counter/timer con - trol (tcon) register is used to enable timer 0 and timer 1 as well as indicate their status. both counter/timers operate in one of four primary modes selected by setting the mode select bits m1-m0 in the counter/timer mode (tmod) register. each timer can be co nfigured independently. following is a detailed description of each operating mode. 22.1.1. mode 0: 13-bit counter/timer timer 0 and timer 1 operate as a 13-bit counter/timer in mode 0. the following describes the configuration and oper - ation of timer 0. however, both timers operate identically and timer 1 is configured in the same manner as described for timer 0. the th0 register holds the eight msbs of the 13-bit counter/timer. tl0 holds the five lsbs in bit positions tl0.4- tl0.0. the three upper bits of tl0 (tl0.7-tl0.5) are inde terminate and should be masked out or ignored when read - ing. as the 13-bit timer register increments and overflows from 0x1fff (all ones) to 0x0000, the timer overflow flag tf0 (tcon.5) is set and an interrupt will occur if enabled. the c/t0 bit (tmod.2) selects the count er/timer's clock source. cl earing c/t selects the syst em clock as the input for the timer. when c/t0 is set to logic 1, high-to-low tran sitions at the selected input pin (t0) increment the timer register. (refer to section ?17.1. ports 0 through 3 and the priority crossbar decoder? on page 163 for informa - tion on selecting and configuring external i/o pins for digital peripherals.) setting the tr0 bit (tcon.4) enables the timer when eith er gate0 (tmod.3) is 0 or the input signal /int0 is logic-level one. setting gate0 to logic 1 allows the timer to be controlled by the external input signal /int0, facili - tating pulse width measurements. setting tr0 does not reset the timer register. the timer register should be initialized to the desired value before enabling the timer. tl1 and th1 form the 13-bit register for timer 1 in the same manner as described above for tl0 and th0. timer 1 is configured and controlled using the relevant tcon and tmod bits just as with timer 0. tr0 gate0 /int0 counter/timer 0xxdisabled 1 0 x enabled 110disabled 111enabled x = don't care
c8051f020/1/2/3 228 rev. 1.4 22.1.2. mode 1: 16-bit counter/timer mode 1 operation is the same as mode 0, except that the counter/t imer registers use all 16 bits. the counter/timers are enabled and configured in mode 1 in the same manner as for mode 0. figure 22.2. t0 mode 0 block diagram tclk tl0 (5 bits) th0 (8 bits) tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt /int0 tr0 t0 crossbar 0 1 0 1 tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 sysclk 12 ckcon t 4 m t 2 m t 1 m t 0 m gate0
c8051f020/1/2/3 rev. 1.4 229 22.1.3. mode 2: 8-bit counter/timer with auto-reload mode 2 configures timer 0 and timer 1 to operate as 8-bit counter/timers with automatic reload of the start value. the tl0 holds the count and th0 holds the reload value. wh en the counter in tl0 overflows from all ones to 0x00, the timer overflow flag tf0 (tcon.5) is set and the counter va lue in tl0 is reloaded from th0. if enabled, an inter - rupt will occur when the tf0 flag is set. the reload value in th0 is not changed. tl0 must be initialized to the desired value before enabling the timer for th e first count to be correct. when in mode 2, timer 1 operates identically to timer 0. both counter/timers are en abled and configured in mode 2 in the same manner as mode 0 . figure 22.3. t0 mode 2 (8-bit auto-reload) block diagram tclk tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt tl0 (8 bits) reload th0 (8 bits) /int0 tr0 t0 crossbar 0 1 0 1 ckcon t 4 m t 2 m t 1 m t 0 m sysclk 12 gate0
c8051f020/1/2/3 230 rev. 1.4 22.1.4. mode 3: two 8-bit counter/timers (timer 0 only) timer 0 and timer 1 behave differently in mode 3. timer 0 is configured as two separate 8-bit counter/timers held in tl0 and th0. the counter/timer in tl0 is controlled using the timer 0 control/status bits in tcon and tmod: tr0, c/t0, gate0 and tf0. it can use ei ther the system clock or an external input signal as its timebase. the timer in the th0 register is restricted to a timer function sourced by the system clock. th0 is enabled using the timer 1 run control bit tr1. th0 sets the timer 1 overflow flag tf1 on overflow and thus controls the timer 1 interrupt. timer 1 is inactive in mode 3, so with timer 0 in mode 3, timer 1 can be turned off and on by switching it into and out of its mode 3. when timer 0 is in mode 3, timer 1 can be operated in modes 0, 1 or 2, but cannot be clocked by external signals nor set the tf1 flag and ge nerate an interrupt. however, the timer 1 overflow can be used to gener - ate the baud clock for uart0 and/or uart1. refer to section ?20. uart0? on page 205 and section ?21. uart1? on page 215 for information on configuring timer 1 for baud rate generation. figure 22.4. t0 mode 3 (two 8-bit timers) block diagram tl0 (8 bits) tmod /int0 tr0 t0 crossbar 0 1 tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt interrupt tr1 th0 (8 bits) t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 ckcon t 4 m t 2 m t 1 m t 0 m 0 1 sysclk 12 gate0
c8051f020/1/2/3 rev. 1.4 231 figure 22.5. tcon: timer control register bit7: tf1: timer 1 overflow flag. set by hardware when timer 1 overflows. this flag can be cleared by software but is automatically cleared when the cpu vectors to th e timer 1 interrupt service routine. 0: no timer 1 overflow detected. 1: timer 1 has overflowed. bit6: tr1: timer 1 run control. 0: timer 1 disabled. 1: timer 1 enabled. bit5: tf0: timer 0 overflow flag. set by hardware when timer 0 overflows. this flag can be cleared by software but is automatically cleared when the cpu vectors to th e timer 0 interrupt service routine. 0: no timer 0 overflow detected. 1: timer 0 has overflowed. bit4: tr0: timer 0 run control. 0: timer 0 disabled. 1: timer 0 enabled. bit3: ie1: external interrupt 1. this flag is set by hardware when an edge/level of type defined by it1 is detected. it can be cleared by software but is automatically cl eared when the cpu vectors to the external interrupt 1 service rou- tine if it1 = 1. this flag is the inverse of th e /int1 input signal's logic level when it1 = 0. bit2: it1: interrupt 1 type select. this bit selects whether the config ured /int1 signal will detect falling edge or active-low level-sensi- tive interrupts. 0: /int1 is level triggered. 1: /int1 is edge triggered. bit1: ie0: external interrupt 0. this flag is set by hardware when an edge/level of type defined by it0 is detected. it can be cleared by software but is automatically cl eared when the cpu vectors to the external interrupt 0 service rou- tine if it0 = 1. this flag is the inverse of th e /int0 input signal's logic level when it0 = 0. bit0: it0: interrupt 0 type select. this bit selects whether the config ured /int0 signal will detect falling edge or active-low level-sensi- tive interrupts. 0: /int0 is level triggered. 1: /int0 is edge triggered. r/w r/w r/w r/w r/w r/w r/w r/w reset value tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0x88
c8051f020/1/2/3 232 rev. 1.4 figure 22.6. tmod: timer mode register bit7: gate1: timer 1 gate control. 0: timer 1 enabled when tr1 = 1 irrespective of /int1 logic level. 1: timer 1 enabled only when tr1 = 1 and /int1 = logic 1. bit6: c/t1: counter/timer 1 select. 0: timer function: timer 1 incremented by clock defined by t1m bit (ckcon.4). 1: counter function: timer 1 incremented by high-to-low transitions on external input pin (t1). bits5-4: t1m1-t1m0: timer 1 mode select. these bits select the timer 1 operation mode. bit3: gate0: timer 0 gate control. 0: timer 0 enabled when tr0 = 1 irrespective of /int0 logic level. 1: timer 0 enabled only when tr0 = 1 and /int0 = logic 1. bit2: c/t0: counter/timer select. 0: timer function: timer 0 incremented by clock defined by t0m bit (ckcon.3). 1: counter function: timer 0 incremented by high-to-low transitions on external input pin (t0). bits1-0: t0m1-t0m0: timer 0 mode select. these bits select the timer 0 operation mode. r/w r/w r/w r/w r/w r/w r/w r/w reset value gate1 c/t1 t1m1 t1m0 gate0 c/t0 t0m1 t0m0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x89 t1m1 t1m0 mode 0 0 mode 0: 13-bit counter/timer 0 1 mode 1: 16-bit counter/timer 1 0 mode 2: 8-bit counter/timer with auto-reload 1 1 mode 3: timer 1 inactive t0m1 t0m0 mode 0 0 mode 0: 13-bit counter/timer 0 1 mode 1: 16-bit counter/timer 1 0 mode 2: 8-bit counter/timer with auto-reload 1 1 mode 3: two 8-bit counter/timers
c8051f020/1/2/3 rev. 1.4 233 figure 22.7. tl0: timer 0 low byte bits 7-0: tl0: timer 0 low byte. the tl0 register is the low byte of the 16-bit timer 0. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8a figure 22.8. tl1: timer 1 low byte bits 7-0: th0: timer 0 high byte. the th0 register is the low byte of the 16-bit timer 1. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8b bits 7-0: th0: timer 0 high byte. the th0 register is the high byte of the 16-bit timer 0. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8c figure 22.9. th0 timer 0 high byte figure 22.10. th1: timer 1 high byte bits 7-0: th1: timer 1 high byte. the th1 register is the high byte of the 16-bit timer 1. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8d
c8051f020/1/2/3 234 rev. 1.4 22.1. timer 2 timer 2 is a 16-bit counter/timer formed by the two 8-bit sfrs: tl2 (low byte) and th2 (high byte). as with timers 0 and 1, timer 2 can use either the system clock or transitions on an external input pin (t2) as its clock source. the counter/timer select bit c/t2 bit (t2con.1) selects the clock source for timer 2. clearing c/t2 selects the system clock as the input for the timer (divided by either one or twelve as specified by the timer clock select bit t2m in ckcon). when c/t2 is set to 1, high-to-low trans itions at the t2 input pin increment the counter/timer reg - ister. (refer to section ?17.1. ports 0 through 3 and the priority crossbar decoder? on page 163 for information on selecting and configuring external i/ o pins for digital peripherals.) timer 2 can also be used to start an adc data conversion. timer 2 offers capabilities not found in timer 0 and timer 1. it operates in one of three modes: 16-bit counter/timer with capture, 16-bit counter/timer with auto -reload or baud rate generator mode. timer 2's operating mode is selected by setting configuration bits in the timer 2 control register (t2con). below is a summary of the timer 2 operating modes and the t2con b its used to configure the c ounter/timer. detailed descrip tions of each mode follow. rclk0 tclk0 cp/rl2 tr2 mode 0 0 1 1 16-bit counter/timer with capture 0 0 0 1 16-bit counter/timer with auto-reload 0 1 x 1 baud rate generator for uart0 1 0 x 1 baud rate generator for uart0 1 1 x 1 baud rate generator for uart0 xxx 0off
c8051f020/1/2/3 rev. 1.4 235 22.1.1. mode 0: 16-bit counter/timer with capture in this mode, timer 2 operates as a 16-bit counter/tim er with capture facility. a high -to-low transition on the t2ex input pin causes the following to occur: 1. the 16-bit value in timer 2 (th2, tl2) is loaded into the capture registers (rcap2h, rcap2l). 2. the timer 2 external flag (exf2) is set to ?1?. 3. a timer 2 interrupt is generated if enabled. timer 2 can use either sysclk, sysclk divided by 12, or high- to-low transitions on the t2 input pin as its clock source when operating in capture mode. clearing the c/t2 bit (t2con.1) selects the syst em clock as the input for the timer (divided by one or tw elve as specified by the timer clock select bit t2m in ckcon). when c/t2 is set to logic 1, a high-to-low transition at the t2 input pin increments the counter/timer register. as the 16-bit counter/timer register increments and overflows from 0xffff to 0x0000, the tf2 timer overflow flag (t2con.7) is set and an interrupt will occur if the interrupt is enabled. counter/timer with capture mode is selected by setting the capture/reload select bit cp/rl2 (t2con.0) and the timer 2 run control bit tr2 (t2con.2) to logic 1. the timer 2 external enable exen2 (t2con.3) must also be set to logic 1 to enable a capture. if exen2 is cl eared, transitions on t2ex will be ignored. figure 22.11. t2 mode 0 block diagram tl2 th2 interrupt tclk rcap2l rcap2h capture t2con rclk0 tclk0 exf2 exen2 tr2 c/t2 cp/rl2 tf2 exen2 crossbar t2ex tr2 t2 ckcon t 4 m t 2 m t 1 m t 0 m 0 1 sysclk 12 0 1
c8051f020/1/2/3 236 rev. 1.4 22.1.2. mode 1: 16-bit counter/timer with auto-reload the counter/timer with auto-reload mode sets the tf2 ti mer overflow flag when the counter/timer register over - flows from 0xffff to 0x0000. an interrupt is generated if enabled. on overflow, the 16-bit value held in the two capture registers (rcap2h, rcap2l) is automatically lo aded into the counter/timer register and the timer is restarted. counter/timer with auto-reload mode is selected by clearing the cp/rl2 bit. setting tr2 to logic 1 enables and starts the timer. timer 2 can use either the system clock or transitions on an external input pin (t2) as its clock source, as specified by the c/t2 bit. if exen2 is set to logic 1, a high-to-low transition on t2ex will also cause a timer 2 reload, and a timer 2 interrupt if enabled. if exen2 is logic 0, transitions on t2ex will be ignored . figure 22.12. t2 mo de 1 block diagram tl2 th2 tr2 t2 tclk rcap2l rcap2h reload interrupt t2con rclk0 tclk0 exf2 exen2 tr2 c/t2 cp/rl2 tf2 ckcon t 4 m t 2 m t 1 m t 0 m 0 1 sysclk 12 0 1 exen2 crossbar t2ex
c8051f020/1/2/3 rev. 1.4 237 22.1.3. mode 2: baud rate generator timer 2 can be used as a baud rate generator for uart0 wh en uart0 is operated in modes 1 or 3 (refer to section ?20.1. uart0 operational modes? on page 206 for more information on the uart0 operational modes). in baud rate generator mode, timer 2 works similarly to the auto-reload mode. on overflow, the 16-bit value held in the two capture registers (rcap2h, rcap2l) is automatically loaded into th e counter/timer register . however, the tf2 overflow flag is not set and no interrupt is generated. in stead, the overflow event is used as the input to the uart's shift clock. timer 2 overflows can be selected to generate baud rates for transmit and/or receive independently. the baud rate generator mode is selected by setting rcl k0 (t2con.5) and/or tclk0 (t2con.2) to ?1?. when rclk0 or tclk0 is set to logic 1, timer 2 operates in the auto-reload mode re gardless of the state of the cp/rl2 bit. note that in baud rate generator mode, the timer 2 timebase is the system clock divided by two. when selected as the uart0 baud clock source, timer 2 defines the uart0 baud rate as follows: baud rate = sysclk / ((65536 - [rcap2h, rcap2l] ) * 32) if a different time base is required, setting the c/t2 bit to logic 1 will allow the timebase to be derived from the exter - nal input pin t2. in this case, the baud rate for the uart is calculated as: baud rate = f clk / ( (65536 - [rcap2h, rcap2l] ) * 16) where f clk is the frequency of the signal (tclk) supplied to timer 2 and [rcap2h, rcap2l] is the 16-bit value held in the capture registers. as explained above, in baud rate generator mode, timer 2 does not set the tf2 overflo w flag and therefore cannot generate an interrupt. however, if exen2 is set to logic 1, a high-to-low transition on the t2ex input pin will set the exf2 flag and a timer 2 interrupt will occur if enable d. therefore, the t2ex input may be used as an additional external interrupt source. figure 22.13. t2 mo de 2 block diagram tl2 th2 tr2 t2 sysclk c/t2 2 tclk rcap2l rcap2h reload crossbar timer 2 overflow pcon 0 1 exen2 t2ex interrupt timer 1 overflow t2con rclk0 tclk0 exf2 exen2 tr2 c/t2 cp/rl2 tf2 crossbar 0 1 2 s m o d 0 s m o d 1 s s t a t 0 s s t a t 1 s t o p i d l e rclk0 0 1 16 rx0 clock tclk0 0 1 16 tx0 clock
c8051f020/1/2/3 238 rev. 1.4 bit7: tf2: timer 2 overflow flag. set by hardware when timer 2 overflows. when the timer 2 interrupt is enabled, setting this bit causes the cpu to vector to the timer 2 interrupt service routine. this bit is not automatically cleared by hardware and must be cleared by software. tf2 will not be set when rclk0 and/or tclk0 are logic 1. bit6: exf2: timer 2 external flag. set by hardware when either a capture or reload is caused by a high-to-low transition on the t2ex input pin and exen2 is logic 1. when the timer 2 interrupt is enabled, setting this bit causes the cpu to vector to the timer 2 interrupt service rout ine. this bit is not automatically cleared by hard- ware and must be cleared by software. bit5: rclk0: receive clock flag for uart0. selects which timer is used for the uart0 receive clock in modes 1 or 3. 0: timer 1 overflows used for receive clock. 1: timer 2 overflows used for receive clock. bit4: tclk0: transmit clock flag for uart0. selects which timer is used for the uart0 transmit clock in modes 1 or 3. 0: timer 1 overflows used for transmit clock. 1: timer 2 overflows used for transmit clock. bit3: exen2: timer 2 external enable. enables high-to-low transitions on t2ex to trigger captures or reloads when timer 2 is not operating in baud rate generator mode. 0: high-to-low transitions on t2ex ignored. 1: high-to-low transitions on t2ex cause a capture or reload. bit2: tr2: timer 2 run control. this bit enables/disables timer 2. 0: timer 2 disabled. 1: timer 2 enabled. bit1: c/t2: counter/timer select. 0: timer function: timer 2 incremented by clock defined by t2m (ckcon.5). 1: counter function: timer 2 incremented by high-to-low transitions on external input pin (t2). bit0: cp/rl2: capture/reload select. this bit selects whether timer 2 functions in capture or auto-reload mode. exen2 must be logic 1 for high-to-low transitions on t2ex to be recognized and used to trigger captures or reloads. if rclk0 or tclk0 is set, this bit is ignored and timer 2 will function in auto-reload mode. 0: auto-reload on timer 2 overflow or high-to-low transition at t2ex (exen2 = 1). 1: capture on high-to-low transition at t2ex (exen2 = 1). r/w r/w r/w r/w r/w r/w r/w r/w reset value tf2 exf2 rclk0 tclk0 exen2 tr2 c/t2 cp/rl2 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xc8 figure 22.14. t2con: timer 2 control register
c8051f020/1/2/3 rev. 1.4 239 bits 7-0: rcap2l: timer 2 capture register low byte. the rcap2l register capture s the low byte of timer 2 when timer 2 is configured in capture mode. when timer 2 is configured in auto-reload mode, it holds the low byte of the reload value. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xca figure 22.15. rcap2l: timer 2 capture register low byte figure 22.16. rcap2h: timer 2 capture register high byte bits 7-0: rcap2h: timer 2 capture register high byte. the rcap2h register captures the high byte of time r 2 when timer 2 is configured in capture mode. when timer 2 is configured in auto-reload mode, it holds the high byte of the reload value. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xcb figure 22.17. tl2: timer 2 low byte bits 7-0: tl2: timer 2 low byte. the tl2 register contains the low byte of the 16-bit timer 2. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xcc figure 22.18. th2 timer 2 high byte bits 7-0: th2: timer 2 high byte. the th2 register contains the high byte of the 16-bit timer 2. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xcd
c8051f020/1/2/3 240 rev. 1.4 22.2. timer 3 timer 3 is a 16-bit timer formed by the two 8-bit sfrs, tmr3l (low byte) and tmr3h (high byte). timer 3 may be clocked by the external oscillator source (divided by eight) or the system clock (divided by either one or twelve as specified by the timer 3 clock select bit t3m in the timer 3 control register tmr3cn). timer 3 is always config - ured as an auto-reload timer , with the reload value held in the tmr3 rll (low byte) and tmr3rlh (high byte) reg - isters. the timer 3 external clock source f eature offers a real-time clock (rtc) mode. when bit t3xclk (tmr3cn.0) is set to logic 1, timer 3 is clocked by the external osci llator input (divided by 8) regardless of the system clock selec - tion. this split clock domain allows timer 3 to be clocked by a precision external source while the system clock is derived from the high-speed internal oscillator. when t3xclk is logic 0, the timer 3 clock source is specified by bit t3m (tmr3cn.1). timer 3 can also be used to start an adc data conversion, for smbus timing (see section ?18. system man - agement bus / i2c bus (smbus0)? on page 183 ), or as a general-purpose timer. timer 3 does not have a counter mode. figure 22.19. timer 3 block diagram tmr3l tmr3h tr3 tclk tmr3rll tmr3rlh reload interrupt toe scl (from smbus) (to adc) crossbar tmr3cn tr3 t3m tf3 t3xclk 1 0 t3xclk sysclk 12 t3m 8 external oscillator source 1 0
c8051f020/1/2/3 rev. 1.4 241 figure 22.20. tmr3cn: timer 3 control register bit7: tf3: timer3 overflow flag. set by hardware when timer 3 overflows from 0xf fff to 0x0000. when the timer 3 interrupt is enabled, setting this bit causes the cpu to vector to the timer 3 interrupt service routine. this bit is not automatically cleared by hardware and must be cleared by software. bits6-3: unused. read = 0000b, write = don't care. bit2: tr3: timer 3 run control. this bit enables/disables timer 3. 0: timer 3 disabled. 1: timer 3 enabled. bit1: t3m: timer 3 clock select. this bit controls the division of the system clock supplied to counter/timer 3. 0: counter/timer 3 uses the system clock divided by 12. 1: counter/timer 3 uses the system clock. bit0: t3xclk: timer 3 external clock select this bit selects the external oscillator input divided by 8 as the timer 3 clock source. when t3xclk is logic 1, bit t3m (tmr3cn.1) is ignored. 0: timer 3 clock source defined by bit t3m (tmr3cn.1). 1: timer 3 clock source is the extern al oscillator input divided by 8. r/w r/w r/w r/w r/w r/w r/w r/w reset value tf3 - - - - tr3 t3m t3xclk 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x91 figure 22.21. tmr3rll: timer 3 reload register low byte bits 7-0: tmr3rll: timer 3 reload register low byte. timer 3 is configured as an auto-reload timer. this register holds the low byte of the reload value. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x92
c8051f020/1/2/3 242 rev. 1.4 figure 22.22. tmr3rlh: timer 3 reload register high byte bits 7-0: tmr3rlh: timer 3 re load register high byte. timer 3 is configured as an auto-reload timer. th is register holds the high byte of the reload value. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x93 figure 22.23. tmr3l: timer 3 low byte bits 7-0: tmr3l: timer 3 low byte. the tmr3l register is the low byte of timer 3. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x94 figure 22.24. tmr3h: timer 3 high byte bits 7-0: tmr3h: timer 3 high byte. the tmr3h register is the high byte of timer 3. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x95
c8051f020/1/2/3 rev. 1.4 243 22.3. timer 4 timer 4 is a 16-bit counter/timer formed by the two 8-bit sfrs: tl4 (low byte) and th4 (high byte). as with timers 0 and 1, timer 4 can use either the system clock or transitions on an external input pin (t4) as its clock source. the counter/timer select bit c/t4 bit (t4con.1) selects the clock source for timer 4. clearing c/t4 selects the system clock as the input for the timer (divided by either one or twelve as specified by the timer clock select bit t4m in ckcon). when c/t4 is set to 1, high-to-low trans itions at the t4 input pin increment the counter/timer reg - ister. refer to section ?17.1. ports 0 through 3 and the priority crossbar decoder? on page 163 for information on selecting and configuring external i/o pins for digital peripherals. timer 4 offers capabilities not found in timer 0 and timer 1. it operates in one of three modes: 16-bit counter/timer with capture, 16-bit counter/timer with auto -reload or baud rate generator mode. timer 4's operating mode is selected by setting configuration bits in the timer 4 control register (t4con). below is a summary of the timer 4 operating modes and the t4con b its used to configure the c ounter/timer. detailed descrip tions of each mode follow. rclk1 tclk1 cp/rl4 tr4 mode 0 0 1 1 16-bit counter/timer with capture 0 0 0 1 16-bit counter/timer with auto-reload 0 1 x 1 baud rate generator for uart1 1 0 x 1 baud rate generator for uart1 1 1 x 1 baud rate generator for uart1 xxx 0off
c8051f020/1/2/3 244 rev. 1.4 22.3.1. mode 0: 16-bit counter/timer with capture in this mode, timer 4 operates as a 16-bit counter/tim er with capture facility. a high -to-low transition on the t4ex input pin causes the following to occur: 1. the 16-bit value in timer 4 (th4, tl4) is loaded into the capture registers (rcap4h, rcap4l). 2. the timer 4 external flag (exf2) is set to ?1?. 3. a timer 4 interrupt is generated if enabled. timer 4 can use either sysclk, sysclk divided by 12, or high- to-low transitions on the t4 input pin as its clock source when operating in capture mode. clearing the c/t4 bit (t4con.1) selects the syst em clock as the input for the timer (divided by one or tw elve as specified by the timer clock select bit t4m in ckcon). when c/t4 is set to logic 1, a high-to-low transition at the t4 input pin increments the counter/timer register. as the 16-bit counter/timer register increments and overflows from 0xffff to 0x0000, the tf4 timer overflow flag (t4con.7) is set and an interrupt will occur if the interrupt is enabled. counter/timer with capture mode is selected by setting the capture/reload select bit cp/rl4 (t4con.0) and the timer 4 run control bit tr4 (t4con.2) to logic 1. the timer 4 external enable exen4 (t4con.3) must also be set to logic 1 to enable a capture. if exen4 is cl eared, transitions on t4ex will be ignored. figure 22.25. t4 mo de 0 block diagram tl4 th4 interrupt tclk rcap4l rcap4h capture t4con rclk0 tclk0 exf4 exen4 tr4 c/t4 cp/rl4 tf4 exen4 crossbar t4ex tr4 t4 ckcon t 4 m t 2 m t 1 m t 0 m 0 1 sysclk 12 0 1
c8051f020/1/2/3 rev. 1.4 245 22.3.2. mode 1: 16-bit counter/timer with auto-reload the counter/timer with auto-reload mode sets the tf4 ti mer overflow flag when the counter/timer register over - flows from 0xffff to 0x0000. an interrupt is generated if enabled. on overflow, the 16-bit value held in the two capture registers (rcap4h, rcap4l) is automatically lo aded into the counter/timer register and the timer is restarted. counter/timer with auto-reload mode is selected by clearing the cp/rl4 bit. setting tr4 to logic 1 enables and starts the timer. timer 4 can use either the system clock or transitions on an external input pin (t2) as its clock source, as specified by the c/t4 bit. if exen4 is set to logic 1, a high-to-low transition on t4ex will also cause a timer 4 reload, and a timer 4 interrupt if enabled. if exen4 is logic 0, transitions on t4ex will be ignored . figure 22.26. t4 mo de 1 block diagram tl4 th4 tr4 t4 tclk rcap4l rcap4h reload interrupt t4con rclk0 tclk0 exf4 exen4 tr4 c/t4 cp/rl4 tf4 ckcon t 4 m t 2 m t 1 m t 0 m 0 1 sysclk 12 0 1 exen4 crossbar t4ex
c8051f020/1/2/3 246 rev. 1.4 22.3.3. mode 2: baud rate generator timer 4 can be used as a baud rate generator for uart1 wh en uart1 is operated in modes 1 or 3 (refer to section ?21.1. uart1 operational modes? on page 216 for more information on the uart1 operational modes). in baud rate generator mode, timer 4 works similarly to the auto-reload mode. on overflow, the 16-bit value held in the two capture registers (rcap4h, rcap4l) is automatically loaded into th e counter/timer register . however, the tf4 overflow flag is not set and no interrupt is generated. in stead, the overflow event is used as the input to the uart's shift clock. timer 4 overflows can be selected to generate baud rates for transmit and/or receive independently. the baud rate generator mode is selected by setting rcl k1 (t4con.5) and/or tclk1 (t4con.4) to ?1?. when rclk1 or tclk1 is set to logic 1, timer 4 operates in the auto-reload mode re gardless of the state of the cp/rl4 bit. note that in baud rate generator mode, the timer 4 timebase is the system clock divided by two. when selected as the uart1 baud clock source, timer 4 defines the uart1 baud rate as follows: baud rate = sysclk / ((65536 - [rcap4h, rcap4l] ) * 32) if a different time base is required, setting the c/t4 bit to logic 1 will allow the timebase to be derived from the exter - nal input pin t4. in this case, the baud rate for the uart is calculated as: baud rate = f clk / ( (65536 - [rcap4h, rcap4l] ) * 16) where f clk is the frequency of the signal (tclk) supplied to timer 4 and [rcap4h, rcap4l] is the 16-bit value held in the capture registers. as explained above, in baud rate generator mode, timer 4 does not set the tf4 overflo w flag and therefore cannot generate an interrupt. however, if exen4 is set to logic 1, a high-to-low transition on the t4ex input pin will set the exf4 flag and a timer 4 interrupt will occur if enable d. therefore, the t4ex input may be used as an additional external interrupt source. figure 22.27. t4 mo de 2 block diagram tl2 th2 tr2 t2 sysclk c/t2 2 tclk rcap2l rcap2h reload rclk0 crossbar timer 2 overflow pcon s m o d 0 s t o p i d l e 0 1 0 1 16 rx0 clock exen2 t2ex interrupt timer 1 overflow t2con rclk0 tclk0 exf2 exen2 tr2 c/t2 cp/rl2 tf2 crossbar 0 1 2 tclk0 0 1 16 tx0 clock
c8051f020/1/2/3 rev. 1.4 247 bit7: tf4: timer 4 overflow flag. set by hardware when timer 4 overflows. when the timer 4 interrupt is enabled, setting this bit causes the cpu to vector to the timer 4 interrupt service routine. this bit is not automatically cleared by hardware and must be cleared by software. tf4 will not be set when rclk1 and/or tclk1 are logic 1. bit6: exf4: timer 4 external flag. set by hardware when either a capture or reload is caused by a high-to-low transition on the t4ex input pin and exen4 is logic 1. when the timer 4 interrupt is enabled, setting this bit causes the cpu to vector to the timer 4 interrupt service rout ine. this bit is not automatically cleared by hard- ware and must be cleared by software. bit5: rclk1: receive clock flag for uart1. selects which timer is used for the uart1 receive clock in modes 1 or 3. 0: timer 1 overflows used for receive clock. 1: timer 4 overflows used for receive clock. bit4: tclk1: transmit clock flag for uart1. selects which timer is used for the uart1 transmit clock in modes 1 or 3. 0: timer 1 overflows used for transmit clock. 1: timer 4 overflows used for transmit clock. bit3: exen4: timer 4 external enable. enables high-to-low transitions on t4ex to trigger captures or reloads when timer 4 is not operating in baud rate generator mode. 0: high-to-low transitions on t4ex ignored. 1: high-to-low transitions on t4ex cause a capture or reload. bit2: tr4: timer 4 run control. this bit enables/disables timer 4. 0: timer 4 disabled. 1: timer 4 enabled. bit1: c/t4: counter/timer select. 0: timer function: timer 4 incremented by clock defined by t4m (ckcon.6). 1: counter function: timer 4 incremented by high-to-low transitions on external input pin (t2). bit0: cp/rl4: capture/reload select. this bit selects whether timer 4 functions in capture or auto-reload mode. exen4 must be logic 1 for high-to-low transitions on t4ex to be recognized and used to trigger captures or reloads. if rclk1 or tclk1 is set, this bit is ignored and timer 4 will function in auto-reload mode. 0: auto-reload on timer 4 overflow or high-to-low transition at t4ex (exen4 = 1). 1: capture on high-to-low transition at t4ex (exen4 = 1). r/w r/w r/w r/w r/w r/w r/w r/w reset value tf4 exf4 rclk1 tclk1 exen4 tr4 c/t4 cp/rl4 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc9 figure 22.28. t4con: timer 4 control register
c8051f020/1/2/3 248 rev. 1.4 bits 7-0: rcap4l: timer 4 capture register low byte. the rcap4l register capture s the low byte of timer 4 when timer 4 is configured in capture mode. when timer 4 is configured in auto-reload mode, it holds the low byte of the reload value. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe4 figure 22.29. rcap4l: timer 4 capture register low byte figure 22.30. rcap4h: timer 4 capture register high byte bits 7-0: rcap4h: timer 4 capture register high byte. the rcap4h register captures the high byte of time r 4 when timer 4 is configured in capture mode. when timer 4 is configured in auto-reload mode, it holds the high byte of the reload value. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe5 figure 22.31. tl4: timer 4 low byte bits 7-0: tl4: timer 4 low byte. the tl4 register contains the low byte of the 16-bit timer 4. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf4 figure 22.32. th4 timer 4 high byte bits 7-0: th4: timer 4 high byte. the th4 register contains the high byte of the 16-bit timer 4. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf5
c8051f020/1/2/3 rev. 1.4 249 23. programmable counter array the programmable counter array (pca0) provides enhanced timer functionality while requiring less cpu interven - tion than the standard 8051 counter/timers. pca0 consists of a dedicated 16-bit counter/timer and five 16-bit capture/ compare modules. each capture/compare m odule has its own associated i/o line (cexn) which is routed through the crossbar to port i/ o when enabled (see section ?17.1. ports 0 through 3 and the priority crossbar decoder? on page 163 ). the counter/timer is driven by a programmable timeba se that can select between six inputs as its source: system clock, system clock divided by four, system clock divided by twelve, the external oscillator clock source divided by 8, timer 0 overflow, or an external clock signal on the eci line. each capture/compare module may be configured to operate independently in one of six modes: edge-triggered capture, software timer, high-speed out - put, frequency output, 8-bit pwm, or 16-bit pwm (each is described in section 23.2 ). the pca is configured and controlled through the system controll er's special function registers. the basic pca block diagram is shown in figure 23.1 . figure 23.1. pca block diagram capture/compare module 1 capture/compare module 0 capture/compare module 2 capture/compare module 3 capture/compare module 4 cex1 eci crossbar cex2 cex3 cex4 cex0 port i/o 16-bit counter/timer pca clock mux sysclk/12 sysclk/4 timer 0 overflow eci sysclk external clock/8
c8051f020/1/2/3 250 rev. 1.4 23.1. pca counter/timer the 16-bit pca counter/timer consists of two 8-bit sfrs: pca0l and pca0h. pca0h is the high byte (msb) of the 16-bit counter/timer and pca0l is the low byte (lsb). reading pca0l automatically latches the value of pca0h into a ?snapshot? register; the following pca0h read accesse s this ?snapshot? register. reading the pca0l register first guarantees an accurate reading of the entire 16-bi t pca0 counter. reading pca0h or pca0l does not disturb the counter operation. the cps2-cps0 bits in the pca0md register select the timebase for the counter/timer as shown in table 23.1 . note that in ?external oscillator source divide d by 8? mode, the external oscillator source is synchronized with the system cl ock, and must have a frequency less than or equal to the system clock. when the counter/timer overflows from 0xffff to 0x0000, the counter overflow flag (cf) in pca0md is set to logic 1 and an interrupt request is generated if cf interr upts are enabled. setting the ecf bit in pca0md to logic 1 enables the cf flag to generate an in terrupt request. the cf bit is not auto matically cleared by hardware when the cpu vectors to the interrupt service rou tine, and must be cleared by software (note: pca0 interrupts must be glo - bally enabled before cf interrupts are recognized. pca0 interrupts are globally enabled by setting the ea bit (ie.7) and the epca0 bit in eie1 to logic 1). clearing the cidl bit in the pca0md register allows the pca to continue normal operation while the cpu is in idle mode. table 23.1. pca timebase input options cps2 cps1 cps0 timebase 0 0 0 system clock divided by 12 0 0 1 system clock divided by 4 0 1 0 timer 0 overflow 011 high-to-low transitions on eci ? (max rate = system clock divided by 4) 100 system clock 101 external oscillator source divided by 8 ? ? external oscillator source divided by 8 is synchronized with the system clock. ? the minimum high or low time for the eci input signal is at least 2 system clock cycles. figure 23.2. pca counter/timer block diagram pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 idle 0 1 pca0h pca0l snapshot register to sfr bus overflow to pca interrupt system cf pca0l read to pca modules sysclk/12 sysclk/4 timer 0 overflow eci 000 001 010 011 100 101 sysclk external clock/8 pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 4 c c f 3
c8051f020/1/2/3 rev. 1.4 251 important note about the pca0cn register: if the main pca counter (pca0h : pca0l) overflows during the execution phase of a read-modify-write instruction (bit-wise setb or clr, anl, orl, xrl) that targets the pca0cn register, the cf (counter overflow) bit will not be set. the following steps should be taken when perform - ing a bit-wise operation on the pca0cn register: step 1. disable global interrupts (ea = 0). step 2. read pca0l. this will latch the value of pca0h. step 3. read pca0h, saving the value. step 4. execute the bit-wise operation on ccfn (for example, clr ccf0, or ccf0 = 0;). step 5. read pca0l. step 6. read pca0h, saving the value. step 7. if the value of pca0h read in step 3 is 0x ff and the value for pca0h read in step 6 is 0x00, then manually set the cf bit in software (for example, setb cf, or cf = 1;). step 8. re-enable interrupts (ea = 1).
c8051f020/1/2/3 252 rev. 1.4 23.2. capture/compare modules each module can be configured to op erate independently in one of six operation modes: edge-triggered capture, software timer, high speed output, frequency output, 8- bit pulse width modulator, or 16-bit pulse width modu - lator. each module has special function registers (sfrs) associated with it in the cip- 51 system controller. these registers are used to exchange da ta with a module and configure the module's mode of operation. table 23.2 summarizes the bit settings in the pca0cpmn regist ers used to select the pca0 capture/compare mod - ule?s operating modes. setting the eccfn bit in a pca0cpmn register enables the module's ccfn interrupt. note: pca0 interrupts must be globally enabled before individu al ccfn interrupts are recogni zed. pca0 interrupts are glo - bally enabled by setting the ea bit (ie.7) and the epca0 bit (eie1.3) to logic 1. see figure 23.3 for details on the pca interrupt configuration. table 23.2. pca0cpm register settings fo r pca capture/compare modules pwm16 ecom capp capn mat tog pwm eccf operation mode x x 10000x capture triggered by positive edge on cexn x x 01000x capture triggered by negative edge on cexn x x 11000x capture triggered by transition on cexn x 1 00100x software timer x 1 00110x high speed output x 1 0 0 x 1 1 x frequency output 0 1 0 0 x 0 1 x 8-bit pulse width modulator 1 1 0 0 x 0 1 x 16-bit pulse width modulator x = don?t care figure 23.3. pca interrupt block diagram pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 4 c c f 3 pca0md c i d l e c f c p s 1 c p s 0 c p s 2 0 1 pca module 0 (ccf0) pca module 1 (ccf1) eccf1 0 1 eccf0 0 1 pca module 2 (ccf2) eccf2 0 1 pca module 3 (ccf3) eccf3 0 1 pca module 4 (ccf4) eccf4 pca counter/ timer overflow 0 1 interrupt priority decoder epca0 (eie1.3) 0 1 ea (ie.7) 0 1 pca0cpmn (for n = 0 to 4) p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n
c8051f020/1/2/3 rev. 1.4 253 23.2.1. edge-triggered capture mode in this mode, a valid transition on the cexn pin causes pca0 to capture the value of the pca0 counter/timer and load it into the corresponding modu le's 16-bit capture/compare register (pca0cpln and pca0cphn). the cappn and capnn bits in the pca0cpmn register are used to select the type of transition that triggers the capture: low-to- high transition (positive edge), high-to-low transition (negativ e edge), or either transition (positive or negative edge). when a capture occurs, the capture/comp are flag (ccfn) in pca0cn is set to logic 1 and an interrupt request is generated if ccf interrupts are enable d. the ccfn bit is not automatically cleared by hardware when the cpu vec - tors to the interrupt service routine, and must be cleared by software. note: the cexn input signal must remain high or low for at least 2 system clock cycles in order to be valid. figure 23.4. pca capture mode diagram pca0l pca0cpln pca timebase cexn crossbar port i/o pca0h capture pca0cphn 0 1 0 1 (to ccfn) pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 4 c c f 3 pca interrupt
c8051f020/1/2/3 254 rev. 1.4 23.2.2. software timer (compare) mode in software timer mode, the pca0 counter/timer is comp ared to the module's 16-bit capture/compare register (pca0cphn and pca0cpln). wh en a match occurs, the capture/compare fl ag (ccfn) in pca0cn is set to logic 1 and an interrupt request is generated if ccf interrupts are enabled. the ccfn bit is not automatically cleared by hardware when the cpu vectors to the interrupt service routine, and must be cleared by software. setting the ecomn and matn bits in the pca0cpmn register enables software timer mode. important note about ca pture/compare registers : when writing a 16-bit value to the pca0 capture/compare registers, the low byte should always be written first. wr iting to pca0cpln clears the ecomn bit to ?0?; writing to pca0cphn sets ecomn to ?1?. figure 23.5. pca software timer mode diagram match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln 00 00 0 1 x enb enb 0 1 write to pca0cpln write to pca0cphn reset pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 4 c c f 3 pca interrupt
c8051f020/1/2/3 rev. 1.4 255 23.2.3. high speed output mode in high speed out put mode, a module?s associated cexn pin is toggled each time a match occurs between the pca counter and the module's 16-bit capture/compare regist er (pca0cphn and pca0cpln) setting the togn, matn, and ecomn bits in the pca0cpmn register enables the high-speed output mode. important note about ca pture/compare registers : when writing a 16-bit value to the pca0 capture/compare registers, the low byte should always be written first. wr iting to pca0cpln clears the ecomn bit to ?0?; writing to pca0cphn sets ecomn to ?1?. figure 23.6. pca high speed output mode diagram match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln 0 1 00 0x enb enb 0 1 write to pca0cpln write to pca0cphn reset pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x cexn crossbar port i/o toggle 0 1 togn pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 4 c c f 3 pca interrupt
c8051f020/1/2/3 256 rev. 1.4 23.2.4. frequency output mode frequency output mode produces a pr ogrammable-frequency square wave on the module?s associated cexn pin. the capture/compare module high byte holds the number of pca clocks to count before the output is toggled. the frequency of the square wave is then defined by equation 23.1 . note: a value of 0x00 in the pca0cphn register is equal to 256 for this equation. where f pca is the frequency of the clock selected by the c ps2-0 bits in the pca mode register, pca0md. the lower byte of the capture/compare module is compared to the pca0 counter low byte; on a match, cexn is toggled and the offset held in the high byte is added to the matc hed value in pca0cpln. frequency output mode is enabled by setting the ecomn, togn, and pwmn bits in the pca0cpmn register. equation 23.1. square wave frequency output f cexn f pca 2 pca 0 cphn ------------------- --------------------- - = 8-bit comparator pca0l enable pca timebase match pca0cphn 8-bit adder pca0cpln adder enable cexn crossbar port i/o toggle 0 1 togn 000 x pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x enb enb 0 1 write to pca0cpln write to pca0cphn reset figure 23.7. pca frequency output mode
c8051f020/1/2/3 rev. 1.4 257 23.2.5. 8-bit pulse width modulator mode each module can be used independently to generate pulse width modulated (pwm) output s on its associated cexn pin. the frequency of the output is dependent on the timebase for the pca0 counter/timer. the duty cycle of the pwm output signal is varied using the module's pca0cpln capture/compare register. when the value in the low byte of the pca0 counter/timer (pca0l) is equal to the value in pca0cpln, the output on the cexn pin will be asserted high. when the count value in pca0l over flows, the cexn output will be asserted low (see figure 23.8 ). also, when the counter/timer low byte (pca0l) overflows from 0xff to 0x00, pca0cpln is reloaded automatically with the value stored in the counter/timer's high byte (pca0h) without software intervention. setting the ecomn and pwmn bits in the pca0cpmn register enables 8-bit pulse width modulator mode. the duty cycle for 8-bit pwm mode is given by equation 23.2 . important note about ca pture/compare registers : when writing a 16-bit value to the pca0 capture/compare registers, the low byte should always be written first. wr iting to pca0cpln clears the ecomn bit to ?0?; writing to pca0cphn sets ecomn to ?1?. using equation 23.2 , the largest duty cycle is 100% (pca0cphn = 0), and the smallest duty cycle is 0.39% (pca0cphn = 0xff). a 0% duty cycle may be generated by clearing the ecomn bit to ?0?. dutycycle 256 pca 0 cphn ? () 256 ------------------ ----------------- ---------------- = equation 23.2. 8-bit pwm duty cycle 8-bit comparator pca0l pca0cpln pca0cphn cexn enable overflow pca timebase 00x0 x q q set clr s r match pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 0 enb enb 0 1 write to pca0cpln write to pca0cphn reset crossbar port i/o figure 23.8. pca 8-bit pwm mode diagram
c8051f020/1/2/3 258 rev. 1.4 23.2.6. 16-bit pulse width modulator mode each pca0 module may also be operat ed in 16-bit pwm mode. in this mode, the 16-bit capture/compare module defines the number of pca0 clocks for the low time of th e pwm signal. when the pca0 counter matches the module contents, the output on cexn is asserted high; when the counter overflows, cexn is asserted low. to output a vary - ing duty cycle, new value writes should be synchronized with pca0 ccfn match interrupts. 16-bit pwm mode is enabled by setting the ecomn, pwmn, and pwm16n bits in the pca0cpmn register. for a varying duty cycle, ccfn should also be set to logic 1 to enable match inte rrupts. the duty cycle for 16-bit pwm mode is given by equation 23.3 . important note about ca pture/compare registers : when writing a 16-bit value to the pca0 capture/compare registers, the low byte should always be written first. wr iting to pca0cpln clears the ecomn bit to ?0?; writing to pca0cphn sets ecomn to ?1? using equation 23.3 , the largest duty cycle is 10 0% (pca0cpn = 0), and the smal lest duty cycle is 0.0015% (pca0cpn = 0xffff). a 0% duty cycle may be generated by clearing the ecomn bit to ?0?. equation 23.3. 16-bit pwm duty cycle dutycycle 65536 pca 0 cpn ? () 65536 ------------------ ------------------ ---------------- - = figure 23.9. pca 16-bit pwm mode pca0cpln pca0cphn enable pca timebase 0000 0 pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 1 16-bit comparator cexn crossbar port i/o overflow q q set clr s r match pca0h pca0l
c8051f020/1/2/3 rev. 1.4 259 23.3. register descriptions for pca0 following are detailed descriptions of the special function registers related to the operation of pca0. bit7: cf: pca counter/t imer overflow flag. set by hardware when the pca0 counter/timer overflows from 0xffff to 0x0000. when the counter/timer overflow (cf) interrupt is enabled, setting this bit causes the cpu to vector to the cf interrupt service routine. this bit is not automati cally cleared by hardware and must be cleared by software. see ?important note about the pca0cn register? on page 251. bit6: cr: pca0 counter/timer run control. this bit enables/disables the pca0 counter/timer. 0: pca0 counter/timer disabled. 1: pca0 counter/timer enabled. bit5: unused. read = 0b, write = don't care. bit4: ccf4: pca0 module 4 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf interrupt is enabled, set- ting this bit causes the cpu to vector to the ccf interrupt service routine. this bit is not automati- cally cleared by hardware and must be cleared by software. bit3: ccf3: pca0 module 3 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf interrupt is enabled, set- ting this bit causes the cpu to vector to the ccf interrupt service routine. this bit is not automati- cally cleared by hardware and must be cleared by software. bit2: ccf2: pca0 module 2 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf interrupt is enabled, set- ting this bit causes the cpu to vector to the ccf interrupt service routine. this bit is not automati- cally cleared by hardware and must be cleared by software. bit1: ccf1: pca0 module 1 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf interrupt is enabled, set- ting this bit causes the cpu to vector to the ccf interrupt service routine. this bit is not automati- cally cleared by hardware and must be cleared by software. bit0: ccf0: pca0 module 0 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf interrupt is enabled, set- ting this bit causes the cpu to vector to the ccf interrupt service routine. this bit is not automati- cally cleared by hardware and must be cleared by software. r/w r/w r/w r/w r/w r/w r/w r/w reset value cf cr - ccf4 ccf3 ccf2 ccf1 ccf0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xd8 figure 23.10. pca0cn: pca control register
c8051f020/1/2/3 260 rev. 1.4 figure 23.11. pca0md: pca0 mode register bit7: cidl: pca0 counter/timer idle control. specifies pca0 behavior when cpu is in idle mode. 0: pca0 continues to function normally while the system controller is in idle mode. 1: pca0 operation is suspended while the system controller is in idle mode. bits6-4: unused. read = 000b, write = don't care. bits3-1: cps2-cps0: pca0 counter/timer pulse select. these bits select the timebas e source for the pca0 counter bit0: ecf: pca counter/timer overflow interrupt enable. this bit sets the masking of the pca0 counter/timer overflow (cf) interrupt. 0: disable the cf interrupt. 1: enable a pca0 counter/timer overflow in terrupt request when cf (pca0cn.7) is set. r/w r/w r/w r/w r/w r/w r/w r/w reset value cidl - cps2 cps1 cps0 ecf 01000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xd9 cps2 cps1 cps0 timebase 0 0 0 system clock divided by 12 0 0 1 system clock divided by 4 0 1 0 timer 0 overflow 011 high-to-low transitions on eci ? (max rate = system clock divided by 4) 1 0 0 system clock 101 external clock divided by 8 ? 1 1 0 reserved 1 1 1 reserved ? the minimum high or low time for the eci input signal is at least 2 system clock cycles. ? external oscillator source divided by 8 is synchronized with the system clock.
c8051f020/1/2/3 rev. 1.4 261 f i gure 23 . 12 . p ca0c pmn: p ca0 c apture /c ompare mode reg i sters pca0cpmn address: pca0 cpm0 = 0xda (n = 0) pca0cpm1 = 0xdb (n = 1) pca0cpm2 = 0xdc (n = 2) pca0cpm3 = 0xdd (n = 3) pca0cpm4 = 0xde (n = 4) bit7: pwm16n: 16-bit pulse width modulation enable this bit selects 16-bit mode when pulse width modulation mode is enabled (pwmn = 1). 0: 8-bit pwm selected. 1: 16-bit pwm selected. bit6: ecomn: comparator function enable. this bit enables/disables the compar ator function for pca0 module n. 0: disabled. 1: enabled. bit5: cappn: capture positive function enable. this bit enables/disables the positive edge capture for pca0 module n. 0: disabled. 1: enabled. bit4: capnn: capture negative function enable. this bit enables/disables the negative edge capture for pca0 module n. 0: disabled. 1: enabled. bit3: matn: match function enable. this bit enables/disables the match function for pca0 module n. when enabled, matches of the pca0 counter with a module's capture/compare regi ster cause the ccfn bit in pca0md register to be set to logic 1. 0: disabled. 1: enabled. bit2: togn: toggle function enable. this bit enables/disables the toggle function for pca0 module n. when enabled, matches of the pca0 counter with a module's capture/compare register cause the logic level on the cexn pin to tog- gle. if the pwmn bit is also set to logic 1, the module operates in frequency output mode. 0: disabled. 1: enabled. bit1: pwmn: pulse width modulation mode enable. this bit enables/disables the pwm function for pca0 module n. when enabled, a pulse width modu- lated signal is output on the cexn pin. 8-bit pwm is used if pwm16n is logic 0; 16-bit mode is used if pwm16n logic 1. if the togn bit is also set, the module operates in frequency output mode. 0: disabled. 1: enabled. bit0: eccfn: capture/compar e flag interrupt enable. this bit sets the masking of the capt ure/compare flag ( ccfn) interrupt. 0: disable ccfn interrupts. 1: enable a capture/compare flag in terrupt request when ccfn is set. r/w r/w r/w r/w r/w r/w r/w r/w reset value pwm16n ecomn cappn capnn matn togn pwmn eccfn 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xda-0xde
c8051f020/1/2/3 262 rev. 1.4 bits 7-0: pca0l: pca0 counter/timer low byte. the pca0l register holds the low byte (lsb) of the 16-bit pca0 counter/timer. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe9 f i gure 23 . 13 . p ca0 l: p ca0 c ounter / t i mer low byte bits 7-0: pca0h: pca0 counter/timer high byte. the pca0h register holds the high byte (msb) of the 16-bit pca0 counter/timer. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf9 figure 23.14. pca0h: pca0 counter/timer high byte
c8051f020/1/2/3 rev. 1.4 263 figure 23.15. pca0cpln: pca0 capture module low byte pca0cpln address: pca0cpl0 = 0xea (n = 0) pca0cpl1 = 0xeb (n = 1) pca0cpl2 = 0xec (n = 2) pca0cpl3 = 0xed (n = 3) pca0cpl4 = 0xee (n = 4) bits7-0: pca0cpln: pca0 capture module low byte. the pca0cpln register hold s the low byte (lsb) of the 16-bit capture module n. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xea - 0xee pca0cphn address: pca0cph0 = 0xfa (n = 0) pca0cph1 = 0xfb (n = 1) pca0cph2 = 0xfc (n = 2) pca0cph3 = 0xfd (n = 3) pca0cph4 = 0xfe (n = 4) bits7-0: pca0cphn: pca0 capture module high byte. the pca0cphn register holds the high byte (msb) of the 16-bit capture module n. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xfa - 0xfe figure 23.16. pca0cphn: pca0 capture module high byte
c8051f020/1/2/3 264 rev. 1.4 notes
c8051f020/1/2/3 rev. 1.4 265 24. jtag (ieee 1149.1) each mcu has an on-chip jtag interface and logic to suppo rt boundary scan for production and in-system testing, flash read/write operations, an d non-intrusive in-circu it debug. the jtag interface is fully compliant with the ieee 1149.1 specification. refer to this sp ecification for detailed descriptions of the test interface and boundary-scan architecture. access of the jt ag instruction register (ir) and data regi sters (dr) are as described in the test access port and operation of the ieee 1149.1 specification. the jtag interface is accessed via four dedicated pins on the mcu: tck, tms, tdi, and tdo. through the 16-bit jtag instruction register (ir), any of the seven instructions shown in figure 24.1 can be com - manded. there are three dr?s associated with jtag boundary-scan, and four as sociated with flash read/write oper - ations on the mcu. figure 24.1. ir: jtag instruction register reset value 0x0000 bit15 bit0 ir value instruction description 0x0000 extest selects the boundary data register for control and observability of all device pins 0x0002 sample/ preload selects the boundary data register for observability and pres etting the scan-path latches 0x0004 idcode selects device id register 0xffff bypass selects bypass data register 0x0082 flash control selects flashcon register to control how the interface logic responds to reads and writes to the flashdat register 0x0083 flash data selects flashdat register fo r reads and writes to the flash memory 0x0084 flash address selects flashadr register which holds the address of all flas h read, write, and erase operations
c8051f020/1/2/3 266 rev. 1.4 24.1. boundary scan the dr in the boundary scan path is an 134-bit shift re gister. the boundary dr provides control and observability of all the device pins as well as the sfr bus and w eak pullup feature via the ex test and sample commands. table 24.1. boundary data register bit definitions extest provides access to both capture and update actions, while sample only performs a capture. bit action target 0 capture reset enable from mcu (c8051f021/3 devices) update reset enable to /rst pin (c8051f021/3 devices) 1 capture reset input from /rst pin (c8051f021/3 devices) update reset output to /rst pin (c8051f021/3 devices) 2 capture reset enable from mcu (c8051f020/2 devices) update reset enable to /rst pin (c8051f020/2 devices) 3 capture reset input from /rst pin (c8051f020/2 devices) update reset output to /rst pin (c8051f020/2 devices) 4 capture external clock from xtal1 pin update not used 5 capture weak pullup enable from mcu update weak pullup enable to port pins 6, 8, 10, 12, 14, 16, 18, 20 capture p0.n output enable from mcu (e.g. bit6=p0.0, bit8=p0.1, etc.) update p0.n output enable to pin (e.g . bit6=p0.0oe, bi t8=p0.1oe, etc.) 7, 9, 11, 13, 15, 17, 19, 21 capture p0.n input from pin (e.g. bit7=p0.0, bit9=p0.1, etc.) update p0.n output to pin (e.g. bit7=p0.0, bit9=p0.1, etc.) 22, 24, 26, 28, 30, 32, 34, 36 capture p1.n output enable from mcu update p1.n output enable to pin 23, 25, 27, 29, 31, 33, 35, 37 capture p1.n input from pin update p1.n output to pin 38, 40, 42, 44, 46, 48, 50, 52 capture p2.n output enable from mcu update p2.n output enable to pin 39, 41, 43, 45, 47, 49, 51, 53 capture p2.n input from pin update p2.n output to pin 54, 56, 58, 60, 62, 64, 66, 68 capture p3.n output enable from mcu update p3.n output enable to pin 55, 57, 59, 61, 63, 65, 67, 69 capture p3.n input from pin update p3.n output to pin 70, 72, 74, 76, 78, 80, 82, 84 capture p4.n output enable from mcu update p4.n output enable to pin 71, 73, 75, 77, 79, 81, 83, 85 capture p4.n input from pin update p4.n output to pin 86, 88, 90, 92, 94, 96, 98, 100 capture p5.n output enable from mcu update p5.n output enable to pin 87, 89, 91, 93, 95, 97, 99, 101 capture p5.n input from pin update p5.n output to pin 102, 104, 106, 108, 110, 112, 114, 116 capture p6.n output enable from mcu update p6.n output enable to pin 103, 105, 107, 109, 111, 113, 115, 117 capture p6.n input from pin update p6.n output to pin
c8051f020/1/2/3 rev. 1.4 267 24.1.1. extest instruction the extest instruction is accessed via the ir. the boundary dr provides control and observability of all the device pins as well as the weak pullup feature. all inputs to on-chip logic are set to logic 1. 24.1.2. sample instruction the sample instruction is accessed via the ir. the boundary dr provides observability and presetting of the scan- path latches. 24.1.3. bypass instruction the bypass instruction is accessed via the ir. it provides access to the st andard jtag bypass data register. 24.1.4. idcode instruction the idcode instruction is accessed via the ir. it provides access to the 32-bit device id register. bit action target 118, 120, 122, 124, 126, 128, 130, 132 capture p7.n output enable from mcu update p7.n output enable to pin 119, 121, 123, 125, 127, 129, 131, 133 capture p7.n input from pin update p7.n output to pin table 24.1. boundary data register bit definitions figure 24.2. deviceid: jtag device id register version = 0000b part number = 0000 0000 0000 0011b (c8051f020/1/2/3) manufacturer id = 0010 0100 001b (silicon labs) reset value version part number manufacturer id 1 0xn0003243 bit31 bit28 bit27 bit12 bit11 bit1 bit0
c8051f020/1/2/3 268 rev. 1.4 24.2. flash programming commands the flash memory can be programmed di rectly over the jtag interface using the flash control, flash data, flash address, and flash scale regi sters. these indirect data registers are accessed via the jtag instruction register. read and write operations on indirect data registers are pe rformed by first setting the ap propriate dr address in the ir register. each read or write is then initiated by writi ng the appropriate indirect operation code (indopcode) to the selected data register. incoming commands to this register have the following format: indopcode: these bit set the operation to perform accordin g to the following table: the poll operation is used to check the busy bit as described below. although a capture-dr is performed, no update-dr is allowed for the poll oper ation. since updates are disabled, polli ng can be accomplished by shifting in/ out a single bit. the read operation initiates a read from the register addre ssed by the draddress. reads can be initiated by shifting only 2 bits into the indirect register. afte r the read operation is initiated, polling of the busy bit must be performed to determine when the operation is complete. the write operation initiates a write of writedata to the register addressed by draddress. registers of any width up to 18 bits can be written. if the register to be written cont ains fewer than 18 bits, the data in writedata should be left- justified, i.e. its msb should occupy bit 17 above. this allo ws shorter registers to be written in fewer jtag clock cycles. for example, an 8-bit re gister could be written by shifting only 10 bi ts. after a write is initiated, the busy bit should be polled to determine when the next operation can be initiated. the contents of the instruction register should not be altered while either a read or write operation is busy. outgoing data from the indirect data register has the following format: the busy bit indicates that the current operation is not complete. it goes high when an operation is initiated and returns low when complete. read and writ e commands are ignored while busy is high. in fact, if polling for busy to be low will be followed by another read or write operati on, jtag writes of the next operation can be made while checking for busy to be low. they will be ignored until busy is read low, at which time the new operation will ini - tiate. this bit is placed ate bit 0 to allow polling by single-b it shifts. when waiting for a re ad to complete and busy is 0, the following 18 bits can be shifted out to obtain the resulting data. readdata is always right-justified. this allows registers shorter than 18 bits to be r ead using a reduced number of shifts. fo r example, the results from a byte-read requires 9 bit shifts (busy + 8 bits). 19:18 17:0 indopcode writedata indopcode operation 0x poll 10 read 11 write 19 18:1 0 0 readdata busy
c8051f020/1/2/3 rev. 1.4 269 figure 24.3. flashcon: jtag flash control register this register determines how the flash interface logi c will respond to reads and writes to the flashdat register. bit7: sfle: scratchpad flash memory access enable. when this bit is set, flash reads and writes are directed to the 128-byte scratchpad flash sector. when sfle is set to logic 1, flash accesses out of the address range 0x00-0x7f should not be attempted. reads/writes out of this ra nge will yield unpredictable results. 0: flash access directed to the 64k byte program/data flash sector. 1: flash access directed to the 128 byte scratchpad sector. bits6-4: wrmd2-0: write mode select bits. the write mode select bits control how the inte rface logic responds to writes to the flashdat register per the following values: 000: a flashdat write replaces th e data in the fashdat register, but is otherwise ignored. 001: a flashdat write initiates a write of flashdat into the memory address by the flashadr register. flashadr is in cremented by one when complete. 010: a flashdat write initiates an erasure (sets all bytes to 0xff) of the flash page containing the address in flashadr. the data written must be 0xa5 for the erase to occur. flashadr is not affected. if flashadr = 0x7dfe - 0x7dff, the entire user space will be erased (i.e. entire flash memory ex cept for reserved area 0x7e00 - 0x7fff). (all other values for wrmd3-0 are reserved.) bits3-0: rdmd3-0: read mode select bits. the read mode select bits control how the inte rface logic responds to reads to the flashdat reg- ister per the following values: 0000: a flashdat read provides the data in the fashdat register, but is otherwise ignored. 0001: a flashdat read initiates a read of th e byte addressed by the flashadr register if no operation is currently active. this mode is used for block reads. 0010: a flashdat read initiates a read of the byte addressed by flashadr only if no operation is active and any data from a prev ious read has alrea dy been read from flashdat. this mode allows single bytes to be read (or the last byte of a block) without initiating an extra read. (all other values for rdmd3-0 are reserved.) reset value sfle wrmd2 wrmd1 wrmd0 rdmd3 rdmd2 rdmd1 rdmd0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
c8051f020/1/2/3 270 rev. 1.4 figure 24.4. flashadr: jtag flash address register this register holds the address for all jtag flash read , write, and erase operations. th is register autoincrements after each read or write, regardless of whether the operation succeeded or failed. bits15-0: flash operation 16-bit address. reset value 0x0000 bit15 bit0 figure 24.5. flashdat: jt ag flash data register this register is used to read or write data to the flash memory across the jtag interface. bits9-2: data7-0: flash data byte. bit1: fail: flash fail bit. 0: previous flash memory operation was successful. 1: previous flash memory operation failed. us ually indicates the associated memory location was locked. bit0: busy: flash busy bit. 0: flash interface logic is not busy. 1: flash interface logic is processing a reque st. reads or writes while busy = 1 will not initiate another operation reset value 0000000000 bit9 bit0
c8051f020/1/2/3 rev. 1.4 271 24.3. debug support each mcu has on-chip jtag and debug logic that provides non-intrusive, full speed, in-circuit debug support using the production part installed in the end application, via the four pin jtag i/f. silicon labs' debug system supports inspection and modification of memory an d registers, breakpoints, and single stepping. no additional target ram, program memory, or communications channe ls are required. all the digital and analog peripherals are functional and work correctly (remain synchronized) while debugging. the watchdog timer (wdt) is disabled when the mcu is halted during single stepping or at a breakpoint. the c8051f020dk is a developmen t kit with all the ha rdware and software necessary to develop application code and perform in-circuit debug wi th each mcu in the c8051f020 family. each kit includes an inte grated development environment (ide) which has a debugger and integrated 8051 assembler. the kit also includes an rs-232 to jtag interface module referred to as the serial adapter, a targ et application board with a c8051f020 installed, rs-232 and jtag cables, and wall-mount power supply.
c8051f020/1/2/3 272 rev. 1.4 contact information silicon laboratories inc. 4635 boston lane austin, tx 78735 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: productinfo@silabs.com internet: www.silabs.com silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademark s or registered trademarks of their respective holder. the information in this document is believed to be accurate in al l respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no re sponsibility for errors and omissions, and disclaims responsibi lity for any consequen ces resulting from the use of information included herein. additi onally, silicon laborator ies assumes no responsibility for the fun ction- ing of undescribed features or parameters. silicon laboratories re serves the right to make change s without further notice. sili con laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpos e, nor does silicon laboratories assume any liabi lity arising out of the application or use of any product or circuit, and specifi cally disclaims any and all liability, including without limitation consequential or incident al damages. silicon laboratories product s are not designed, intended, or authorized for use in applications in tended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a si tuation where personal injury or death may occur. should buyer purchase or use silicon laboratories prod ucts for any such unintended or unauthorized application, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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